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ICs for Communications ISDN Subscriber Access Controller for Upn-Interface Terminals
SmartLink-P PSB 2197
User's Manual 02.95
PEB 2197 Revision History: Previous Releases: Page
Original Version: 02.95
Subjects (changes since last revision)
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our "Product Overview".
General Information
Table of Contents 1 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 2 2.1 2.1.1 2.1.2 2.1.3 2.1.3.1 2.1.3.2 2.1.3.3 2.1.4 2.1.5 2.1.6 2.1.6.1 2.1.6.2 2.2 2.2.1 2.2.2 2.2.3 2.2.3.1 2.2.3.2 2.2.4 2.2.5 2.3 2.3.1 2.3.2 2.3.3 2.3.3.1 2.3.3.2 2.3.4 2.3.5 2.3.6
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Low Cost Digital Telephone Using the SmartLink-P . . . . . . . . . . . . . . . . .20 Low Cost Digital Feature Phone Using the SmartLink-P . . . . . . . . . . . . . .21 Upn-Terminal Repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Network Termination Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 S/T-Interface Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 HDLC-Controller on IOM(R)-2 Extensions . . . . . . . . . . . . . . . . . . . . . . . . . .25 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Terminal Equipment (TE) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 General Functions and Device Architecture (TE-mode) . . . . . . . . . . . . . .26 Clock Generation (TE-Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Interfaces (TE-Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 IOM(R)-2 Interface in TE-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Upn-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 D-Channel-Arbitration in TE-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 HDLC-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Terminal Specific Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 LCD-Contrast Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Ring Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Terminal Repeater (TR) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 General Functions and Device Architecture (TR-Mode) . . . . . . . . . . . . . .56 Clock Generation (TR-Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Interfaces (TR-Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 IOM(R)-2 Interface in TR-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Upn-lnterface in TR-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 D-Channel-Arbitration in TR-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 HDLC-Controller Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 General Functions and Device Architecture (HDLC-Controller Mode) . . .63 Clock Generation (HDLC-Controller Mode) . . . . . . . . . . . . . . . . . . . . . . . .64 Interfaces (HDLC-Controller Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 IOM(R)-2 Interface in HDLC-Controller Mode . . . . . . . . . . . . . . . . . . . . . . .65 D-Channel-Arbitration in HDLC-Controller Mode . . . . . . . . . . . . . . . . . . .66 HDLC-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Semiconductor Group
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General Information
Table of Contents 3 3.1 3.1.1 3.1.2 3.1.2.1 3.1.2.2 3.1.2.3 3.1.2.4 3.1.2.5 3.1.2.6 3.1.3 3.1.4 3.1.4.1 3.1.4.2 3.1.4.3 3.1.5 3.1.6 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.1.4 3.2.1.5 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 4 4.1 5 6
Page
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 TE-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Interrupt Structure and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Control of the Upn-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Power-Down of the IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Activation/Deactivation of the Upn-lnterface . . . . . . . . . . . . . . . . . . . . . . .68 Layer-1 Command/lndication Codes in TE-Mode . . . . . . . . . . . . . . . . . . .69 State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 TE-Mode State Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Example of the Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Operation of the Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . .75 Control of the HDLC-Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HDLC-Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HDLC-Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Examples for the HDLC-Controller Operation . . . . . . . . . . . . . . . . . . . . . .79 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 TR-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Control of the Upn-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Activation/Deactivation of the IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . .96 Layer-1 Command/Indication Codes in TR-Mode . . . . . . . . . . . . . . . . . . .97 State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 TR-Mode State Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Example of the Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . .101 D-Channel Access Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 HDLC-Controller Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Interrupt Structure and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Control of the Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Control of the HDLC-Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Control of Terminal Specific Functions . . . . . . . . . . . . . . . . . . . . . . . . . .104 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 SmartLink-P Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
IOM(R), IOM(R)-1, IOM(R)-2, SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R), ARCOFI(R) , ARCOFI(R)-BA, ARCOFI(R)-SP, EPIC(R)-1, EPIC(R)-S, ELIC(R), IPAT(R)-2, ITAC(R), ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P, ISAC(R)-P TE, IDEC(R), SICAT(R), OCTAT(R)-P, QUAT(R)-S are registered trademarks of Siemens AG. MUSACTM-A, FALCTM54, IWETM, SARETM, UTPTTM, ASMTM, ASPTM are trademarks of Siemens AG. Purchase of Siemens I2C components conveys a license under the Philips' I2C patent to use the components in the I2C-system provided the system conforms to the I2C specifications defined by Philips. Copyright Philips 1983.
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02.95
General Information
Introduction The PSB 2197, SmartLink-P, implements the subscriber access functions for a digital terminal to be connected to a two-wire Upn-interface. The PSB 2197 SmartLink-P is an optimized device for TE-applications, covering the complete layer-1 and basic layer-2 functions for digital terminals. The PSB 2197 SmartLink-P combines the functions of the Upn-transceiver with reduced loop length (one channel of the OCTAT(R)-P PEB 2096) and a simple HDLC-controller for signaling data onto one chip. A pulse width modulator is included to provide an LCD-contrast control or a ring tone signal. The serial control port of the SmartLink-P is compatible to most serial interfaces of microcontrollers. In addition it provides the microcontroller clock signal as well as an undervoltage detector and reset generation including a watchdog function. The Terminal Repeater function of the SmartLink-P allows to cascade two telephones which are controlled by one Upn-interface from the line card or to extend the loop length by using an IEC-Q transceiver. The SmartLink-P can also be used as a simple HDLC-controller which provides the TIC-bus access procedure. In this mode, the Upn-transceiver is inactive. The PSB 2197 SmartLink-P interfaces to voice/data devices via the IOM(R)-2 interface and provides an additional bit clock and strobe signal for standard codecs. The upstream B-channel information may be muted or loop back the downstream data. The PSB 2197 SmartLink-P is a 1-micron CMOS device offered in a P-DSO-28 package. It operates from a single 5-V supply. Note: Upn in the document refers to a version of the Up0-standard with a reduced loop length.
Semiconductor Group
5
ISDN Subscriber Access Controller for Upn-Interface Terminals (SmartLink-P)
Preliminary Data 1 Features
PSB 2197
CMOS IC
* Cost/performance-optimized Upn-interface transceiver, compatible to PEB 2096 OCTAT-P and PSB 2195 ISAC(R)-P or PSB 2196 ISAC(R)-P TE * HDLC-controller with 2 x 4 byte FIFO per direction * IOM(R)-2 interface for terminal application including bit clock and strobe signal * Uplink MUTE function P-DSO-28-1 * Selective B-channel loop back * Serial control port * Pulse width output LCD-contrast control or ring tone generation * CPU-clock and reset output * Watchdog timer * Test loops * Advanced CMOS-technology * Low power consumption: active: 100 mW max.
Type PSB 2197T
Ordering Code Q67100-H6462
Package P-DSO-28-1 (SMD)
Semiconductor Group
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02.95
Features
Pin Configurations (top view)
P-DSO-28-1
PWO/RING/MODE RST RST VSS LIa Line Interface LIb VDD TR/TE XTAL1 XTAL2 INT TST VSS VDDDET/TCM 1 2 3 4 5 6 7 8 10 11 12 13 14 28 27 26 25 24 23 22 PSB 2197T 21 20 19 18 17 16 15
ITP06294
SDS BCL VDD VSS DCL FSC DD DU MOSI MISO SCLK VDD MCLK CS
Semiconductor Group
7
Features
1.1
Pin No.
Pin Definitions and Functions
TE-Mode TR-Mode HDLCController Mode
Symbol Input (I) Output (O) Open Drain (OD) Function
P-DSO-28
Symbol
Input (I) Output (O) Open Drain (OD)
Symbol
Input (I) Output (O) Open Drain (OD)
15
CS
I
CS
I
CS
I
Chip Select. A low level indicates a microprocessor access to the SmartLink-P. It masks the INT-output. Interrupt Request. INT becomes active if the SmartLink-P requests an interrupt. INT is masked by CS. Microprocessor Clock. Clock output for the microcontroller. Reset. High active reset output. In TRmode and HDLCcontroller mode, RST outputs the inverse of the RST-input. Reset. Low active reset output and input (TE, open drain), low active reset input in TR-mode. Terminal Repeater/ TE-Mode Selection. Selects terminal repeater mode (VDD) or TE-mode (VSS).
11
INT
OD
INT
OD
INT
OD
16
MCLK
O
0, low
O
0, low
O
3
RST
O
inv. RST
O
inv. RST
O
2
RST
I/O (OD)
RST
I
RST
I
8
TR/TE (VSS)
I
TR/TE (VDD)
I
TR/TE (VDD)
I
Semiconductor Group
8
Features
Pin Definitions and Functions (cont'd)
Pin No. TE-Mode TR-Mode HDLCController Mode
Symbol Input (I) Output (O) Open Drain (OD) Function
P-DSO-28
Symbol
Input (I) Output (O) Open Drain (OD)
Symbol
Input (I) Output (O) Open Drain (OD)
20
MOSI
I
MOSI
I
MOSI
I
Master Out Slave In. Receive data line of the serial control interface. Operates only as slave. Master In Slave Out. Transmit data line of the serial control interface. Operates only as slave. MISO is tristate while CS is high. Serial Clock. Clock signal of the serial control interface. Data Downstream. Data Upstream. Transfer the data of the IOM-2 interface. External pull-up resistors in the range of 4.7 k to 820 are required.
19
MISO
O
MISO
O
MISO
O
18
SCLK
I
SCLK
I
SCLK
I
22 21
DD DU
I/O (OD) I/O (OD)
DD DU
I/O (OD) I/O (OD)
DD DU
I/O (OD) I/O (OD)
Semiconductor Group
9
Features
Pin Definitions and Functions (cont'd)
Pin No. TE-Mode TR-Mode HDLCController Mode
Symbol Input (I) Output (O) Open Drain (OD) Function
P-DSO-28
Symbol
Input (I) Output (O) Open Drain (OD)
Symbol
Input (I) Output (O) Open Drain (OD)
9
XTAL1
I
XTAL1 I
XTAL1
I
10
XTAL2
O
XTAL2 O
O
Crystal 1. Connection for a crystal or used as external clock input. For HDLC-controller mode XTAL1 requires a clock signal of at least 80 clock periods after reset. Crystal 2. Connection for a crystal. Not connected if an external clock is supplied on XTAL1. (TE & TR-mode) Data Clock. IOMinterface clock signal. Clock frequency is twice the IOM-data rate. TE: clock output IOM-2: 1536 kHz TR, HDLC: clock input IOM-2: 1536 kHz Frame Sync. TE: Frame synchronization output. High during IOMchannel 0 on the IOM-2 interface. TR, HDLC: Input synchronization signal IOM-2 mode.
24
DCL
O
DCL
I
DCL
I
23
FSC
O
FSC
I
FSC
I
Semiconductor Group
10
Features
Pin Definitions and Functions (cont'd)
Pin No. TE-Mode TR-Mode HDLCController Mode
Symbol Input (I) Output (O) Open Drain (OD) Function
P-DSO-28
Symbol
Input (I) Output (O) Open Drain (OD)
Symbol
Input (I) Output (O) Open Drain (OD)
5 6
Lla Llb
I/O I/O
Lla Llb
I/O I/O
Lla Llb
I/O I/O
Line Interface a. Line Interface b. Upn-transceiver signals. In HDCL-controller mode both pins must be connected via a 10 k resistor. Bit Clock. IOM-bit clock signal (768 kHz) in TE- and HDLC-controller mode if programmed by SDS-bits. In TR-mode, the default value of CTRL4 fixes BCL to `0'. Serial Data Strobe. Strobe signal to indicate 64 kbit/s time-slot in TE- and HDLC-mode. In TR-mode, the default value of CTRL4 fixes SDS to `0'. Pulse Width Output/Ring/Mode. Provides the output of the pulse width modulator or ring tone generator. Selects between HDLC-(1) and TR-(0) mode if TR/TE = 1.
27
BCL
O
0, low
O
BCL
O
28
SDS
O
0, low
O
SDS
O
1
PWO/ RING
O
HDLC/ I TR
HDLC/ TR
I
Semiconductor Group
11
Features
Pin Definitions and Functions (cont'd)
Pin No. TE-Mode TR-Mode HDLCController Mode
Symbol Input (I) Output (O) Open Drain (OD) Function
P-DSO-28
Symbol
Input (I) Output (O) Open Drain (OD)
Symbol
Input (I) Output (O) Open Drain (OD)
14
VDDDET
I
TCM
I
VDDDET
I
VDDDET/T-Channel Mode. In TE- and HDLC-mode, this pin selects if the VDD detection is active (`0') and reset pulses are generated or whether it is deactivated (`1') and an external reset has to apply on pin RST. In TR-mode, TCM is used to select the T-channel source (S/G or `1'). Test Pin. This input is used to select the test mode register via the serial interface. See test mode description. For normal operation, this pin must be tied to high (VDD). Power Supply (+ 5 V 5 % (Upn-specification), 10 % operational). Ground.
12
TST
I
TST
I
TST
I
7, 17, 26
VDD
VDD
VDD
4, 13, 25
VSS
VSS
VSS
Semiconductor Group
12
Features
Please note that pin 4 and pin 7 are the supply pins for the analog drivers Lla/b. They are disconnected internally from the other supply pins except for the ESD-protection circuitry. To overcome ESD-problems it is necessary to put series resistors in the low voltage output drivers. The resistor value is in range 40 to 50 . The following output drivers will have these resistors: INT, MCLK, RST, RST, MISO, BCL, SDS, PWO/Ring/MODE. The resistor doesn't affect the high voltage output driver. The following output drivers will not have the resistors: DD, DU, XTAL2, Lla, Llb.
Semiconductor Group
13
Features
1.2
Logic Symbol
TE-Mode
+5V 0V 15.36 MHz 100 ppm
IOM -2 DD DU FSC DCL SDS BCL
R
VDD
VSS
XTAL1
XTAL2 LI a
U pn
LI b
TST TR/TE VDDDET/TCM INT MCLK RST RST
VDD VSS
VDDDET
PWO/RING SCLK MOSI MISO CS
Microcontroller
ITL06295
Figure 1 Logic Symbol of the SmartLink-P TE-Mode
Semiconductor Group 14
Features
TR-Mode
15.36 MHz 100 ppm 0V +5V
R
XTAL2 U pn LI a
XTAL1
VSS
VDD
IOM -2 DD DU FSC
LI b
DCL TST TR/TE PWO/RING/MODE VDDDET/TCM RST RST SCLK MOSI CS
VDD VDD VSS
TCM
VSS
VSS
VDD
ITL06296
Figure 2 Logic Symbol of the SmartLink-P TR-Mode
Semiconductor Group 15
Features
+5V
0V
HDLC-Controller Mode
80 Clocks During Reset
VDD
IOM -2 DD DU FSC
R
VSS
XTAL1 LI a
LI b TST
DCL TR/TE SDS PWO/RING/MODE BCL VDDDET/TCM SCLK MOSI MISO CS INT RST RST
VDD VDD VDD
VDDDET
Microcontroller
ITL06297
Figure 3 Logic Symbol of the SmartLink-P HDLC-Controller Mode
Semiconductor Group 16
Features
1.3
Functional Block Diagram
TE-Mode IOM -2 / PCM U pn IOM -2 Interface TIC
R R
D-Channel Controller Pulse Width Modulator Ring Tone Generator
U pn Transceiver
FIFO
Serial Control Port
Clock, Reset
ITB06298
Microcontroller
Figure 4 Block Diagram of the SmartLink-P TE-Mode
Semiconductor Group 17
Features
TR-Mode IOM -2 U PN U PN Transceiver TIC IOM -2 Interface
R R
Reset
ITB05321
Figure 5 Block Diagram of the SmartLink-P TR-Mode
Semiconductor Group
18
Features
HDLC-Controller Mode IOM -2
R
D-Channel Controller
IOM -2 Interface TIC
R
FIFO
Serial Control Port
Reset
ITB06299
Microcontroller
Figure 6 Block Diagram of the SmartLink-P HDLC-Controller Mode
Semiconductor Group 19
Features
1.4 1.4.1
System Integration Low Cost Digital Telephone Using the SmartLink-P
A low cost digital telephone behind a PBX consists of the SmartLink-P, a standard codec and a microcontroller with on-chip ROM. This architecture is shown in figure 7. The SmartLink-P performs the conversion between the Upn-interface and the lOM-2 interface of the B-channel and D-channel information. The D-channel signaling information is processed by an HDLC-controller inside the SmartLink-P which provides 2 x 4 byte FlFOs in each direction. The serial strobe signal controls the time-slot which is used by the codec. A frequency signal generated by the SmartLink-P can be used for ring tone generation. The C510 family of microcontrollers are versions of the standard C501 core enhanced by the synchronous serial interface (SSI).
IOM -2/PCM Extensions
R
DU, DD, BCL, SDS or DU, DD, DCL, FSC
Microcontroller
Serial I/O
U pn SmartLink-P
Codec
MC68HC05 SAB C510
PSB 2197
DC/DC
1 4 7 * 2 5 8 0 3 6 9 #
+5 V
Handset
Loudspeaker
Keyboard
LED Matrix
Piezo Ringer
ITS06300
Figure 7 Low Cost Digital Telephone Using the SmartLink-P
Semiconductor Group 20
Features
1.4.2
Low Cost Digital Feature Phone Using the SmartLink-P
A low cost digital feature phone behind a PBX consists of the SmartLink-P, a feature codec like the ARCOFI(R)-SP PSB 2163 and a microcontroller with on-chip ROM. This architecture is shown in figure 8. The SmartLink-P performs the conversion between the Upn-interface and the IOM-2 interface of the B-channel and D-channel information. The D-channel signaling information is processed by an HDLC-controller inside the SmartLink-P which provides 2 x 4 byte FlFOs in each direction. The parallel microcontroller interface is designed in a way to share the control lines with an LCD-display controller reducing the required number of l/O-lines. A pulse width modulated signal can be used to control the contrast of an LCD-display. The C510 family of microcontrollers are versions of the standard C501 core enhanced by the synchronous serial interface (SSI).
Extensions
IOM -2 Serial I/O
R
DU, DD, DCL, FSC
U pn Microcontroller
R
ARCOFI -SP PSB 2163
MC68HC05 SAB C510
SmartLink-P
PSB 2197
DC/DC
1 4 7 * 2 5 8 0 3 6 9 #
SIEMENS HL IT 49-89-4144 LED Matrix LCD Display
+5 V
Handset
LoudMicrospeaker phone
Keyboard
ITS06301
Figure 8 Low Cost Digital Feature Phone Using the SmartLink-P
Semiconductor Group 21
Features
1.4.3
Upn-Terminal Repeater
The SmartLink-P is designed to operate as a Upn-terminal repeater (figure 9). It provides a mechanism to control further Upn-terminals by using the T-channel of the Upn-interface and the TlC-bus on the IOM-2 interface. The terminal repeater function allows to cascade two Upn-telephones up to a loop length of 100 m.
Telephone 1
IOM -2 U pn SmartLink-P TR-Mode ARCOFI -SP or Codec
R
R
SmartLink-P TE-Mode
PSB 2197
Terminal Repeater Plug-IN Board
PSB 2163
Basic-Telephone Board
PSB 2197
LineCard
IOM -2 U pn ARCOFI -SP or Codec
R
R
SmartLink-P TE-Mode
PSB 2163
PSB 2197
Telephone 2
ITS06302
Figure 9 Upn-Terminal Repeater
Semiconductor Group 22
Features
1.4.4
Network Termination Module
The combination of the PEB 2091 (IEC-Q) and PSB 2197 (SmartLink-P) allows the extension of the loop length between the line card and Upn-terminals up to 8 km. The SmartLink-P provides the regular Upn-interface to connect standard Upn-terminals to it.
NT-Module
IOM -2 U 2B1Q SmartLink-P TR-Mode IEC-Q TE-Mode LineCard
R
PSB 2197
PSB 2091
IOM -2 U pn ARCOFI -SP or Codec
R
R
SmartLink-P TE-Mode
PSB 2163
Telephone
PSB 2197
ITS06303
Figure 10 Network Termination Using the SmartLink-P
Semiconductor Group
23
Features
1.4.5
S/T-Interface Option
A telephone based on the SmartLink-P may be extended by an S/T-interface option to connect standard S/T-interface terminals like ISDN PC cards or videophones to it (figure 11). This option uses a PSB 20810 (mask version of the SBCX, PEB 2081) for the S/T-interface. The D-channel arbitration between the D-channel controller of the SmartLink-P and the upstream D-channel data of the S/T-interface is done by the TIC-bus of the IOM-2 interface.
Telephone IOM -2
R
U pn Masked SBCX
PSB 20810
S/T Interface Plug-IN Board
ARCOFI -SP or Codec
R
SmartLink-P
PSB 2163
Basic-Telephone Board
PSB 2197
LineCard
TerminalAdapter V.24, X.21, X.25
ISDN PC-Card
ISDN Videophone
ITS06304
S/T Bus
Figure 11 Upn-Telephone with S/T-Interface Option
Semiconductor Group 24
Features
1.4.6
HDLC-Controller on IOM(R)-2 Extensions
The SmartLink-P can be used as a HDLC-controller to access the D-channel via the TlC-bus procedure. In this mode, the Upn-interface is not active.
Option Board with Requires D-Channel Access
Basic-Telephone Board IOM -2
R
SmartLink-P HDLC-Controller Mode
U pn ARCOFI -SP or Codec
R
SmartLink-P TE-Mode
PSB 2197
PSB 2163
PSB 2197
LineCard
MC 68HC05 Microcontroller
MC 68HC05 Microcontroller
SAB C510
SAB C510
ITS06305
Figure 12 HDLC-Controller on IOM(R)-2 Extensions
Semiconductor Group 25
Functional Description
2
Functional Description
Selection between TE-, TR-Mode and HDLC-Controller Mode The selection between the three operating modes is done via the combination of TR/TE-input and PWO/Ring/Mode input. If TR/TE is connected to VSS (GND), the terminal equipment mode is selected. PWO/Ring/Mode operates as output providing the LCD-contrast or ringing signal. If TR/TE is connected to VDD (+ 5 V), the PWO/Ring/Mode input selects between TR-mode (`0') and HDLC-controller mode (`1'). The TR-mode remains as a stand-alone function with the requirement that CS must be connected to VDD and MOSI should be connected to VSS. If the HDLC-controller mode is selected, the Upn-state machine must reach a defined reset state. Therefore it is necessary to provide a clock signal to XTAL1 which is active during reset and remains active at least 80 clock periods after reset. It is recommended to connect the IOM-2 DCL-signal to XTAL1. 2.1 2.1.1 Terminal Equipment (TE) Mode General Functions and Device Architecture (TE-mode)
Figure 13 depicts the detailed architecture of the PSB 2197 SmartLink-P in TE-mode: * Upn-interface transceiver, functionally fully compatible to both PEB 2095 IBC and PEB 2096 OCTAT-P, also features the terminal repeater mode * Serial control port * Reset and microcontroller clock generation * HDLC-controller with 2 x 4 byte FlFOs per direction * IOM-2 interface for terminal application * MUTE function * B-channel loop on IOM-2 * Pulse width modulator for LCD-contrast control or ring tone generation * Watchdog timer
Semiconductor Group
26
Functional Description
DU DD FSC DCL BCL SDS
IOM -2 Interface
R
LI a LI b
TIC Bus -
PWO
Pulse Width Modulator
HDLC Transmitter
HDLC Receiver
CIO
Timing
DPLL
OSC
15.36 MHz
TR/TE Serial Control Port Reset Logic VDDDET/TCM
SCLK MOSI MISO
CS
INT
RST
RST
MCLK
ITS06306
Figure 13 Device Architecture of the SmartLink in TE-Mode
Semiconductor Group 27
Functional Description
2.1.2
Clock Generation (TE-Mode)
In TE-mode, the oscillator is used to generate a 15.36-MHz clock signal. This signal is used by the DPLL to synchronize the IOM-2 clocks to the received Upn-frames. The oscillator clock is divided by 2 to generate a 7.68-MHz clock which drives the remaining functions. The prescaler for the microcontroller clock divides the 7.68-MHz clock by 1, 2, 4 or 8. The pulse width modulator and the ring tone generator receive their clock signal from a divider which generates a 128-kHz and 32-kHz signal. The later signal is also used to drive the reset/watchdog counter. Note that only the IOM-2 clock signals (FSC, DCL, BCL) may be stopped during the power-down state. The oscillator and the other modules remain active all the time.
DU DD
U pn State Machine
HDLC Controller
TIC Bus Controller (CIO)
IOM -2 Interface FSC
R
15.36 MHz 15.36 MHz OSC :2 7.68 MHz
DPLL
DCL BCL
Prescaler
MCLK
Divider
128 kHz 32 kHz
Pulse Width Ring Tone Reset/ Watchdog
PWO/RING
RST
ITS06307
Figure 14 Clock Generation in TE-Mode
Semiconductor Group 28
Functional Description
2.1.3
Interfaces (TE-Mode)
The PSB 2197 SmartLink-P serves four interfaces in TE-mode: * Serial microcontroller interface for higher layer functions incl. reset and microcontroller clock generation * IOM-2 interface: between layer-1 and layer-2 and as a universal backplane for terminals * Upn-interface towards the two-wire subscriber line * Pulse width modulator/Ringing output 2.1.3.1 Microcontroller Interface The SmartLink-P provides a serial control interface which is compatible to the SPI-interface of Motorola or Siemens C510 family of microcontrollers. Serial Control Interface The SmartLink-P is programmable via a serial control interface. It provides access to the D-channel FlFOs as well as global control/status registers. It consists of 5 lines: SCLK, MOSI, MISO, CS, INT. CS is used to start a serial access to the SmartLink-P registers: Following a falling edge on CS, data is transmitted in groups of eight bits until the CS-line becomes inactive. The data transfer is synchronized by the SCLK-input. MISO changes with the falling edge of SCLK while the contents of MOSI is latched on the rising edge of SCLK. Data is transferred with the MSB first and LSB last. The structure of the serial control interface is designed to provide a fast full duplex data transfer. Two control/status bytes are transferred followed by the data of the HDLC FlFOs. Two additional control bytes can be transferred on request. Figure 15 shows the timing of a serial control interface transfer.
Semiconductor Group
29
Functional Description
CS
SCLK STA1 MISO D7 D6 D5 D4 D3 D2 D1 CTRL1 D0 STA2 or RFIFO
~~ ~~
~ ~
D7 D6 D5 D4 D3 D2 D1 CTRLn or XFIFO
D0
~ ~
MOSI
INT CMDR_ ENABLE
ITD06308
Figure 15 Serial Control Interface Timing The serial control port outputs a status byte (STA1) while the first control byte (CTRL1) is received. This status byte informs whether D-channel information follows and about the transmitter status. Following this byte a second status byte (STA2) is transmitted while the second control byte (CTRL2) is received. Following these two bytes, FlFO-data or additional control bytes may be transmitted. The contents of the RFIFO is transmitted if a receive FlFO-status bit was set (RPF, RME) until a receiver command (RMC, RHR, RMD) has been received. After four bytes have been read, the SmartLink continues to transmit RFIFO data as long as transfers are made (as long as CS is low and clocks are transferred). The contents of the RFIFO will be repeated after 4 bytes. A new FlFO-access continues with the next byte. The CTRL2 byte specifies the number of bytes which have to be transferred into the XFIFO in receive direction. Additional data bytes will be ignored. During transfer of CTRL3 and CTRL4, RFIFO data will not be output.
Semiconductor Group
30
~ ~
x D7 D6 D5 D4 D3 D2 D1
D0
D7 D6 D5 D4 D3 D2 D1
D0
Functional Description
The access to the serial control interface may be stopped at any time by setting the CS-input to `1'. If this happens in the middle of a RFlFO-byte, the information of that byte will be lost. In receive direction, the contents of the shift register will not be written into the XFIFO or the proper register. If the access is stopped during the transfer of RFlFO-data, the SmartLink will output the remaining number of bytes in the next access, but no RFlFO-status bit will be set. Thus, the microcontroller has to monitor the number of transferred bytes. A minimum interval of 10 DCL clock periods (6.5 s) is necessary between serial accesses (rising edge of previous access until falling edge of next access). This time is required to perform the commands entered in the CTRL2-register correctly.
CS 10 x DCL
ITD06309
An earlier access CTRL2-commands.
may
result in an
incorrect execution
of the previous
Figure 16 shows some examples of the data transfer over the serial control interface.
Semiconductor Group
31
Functional Description
CS
MISO
STA1
STA2
RFIFO Byte 1 RFIFO Byte 2 RFIFO Byte 3 RFIFO Byte 4 RFIFO Byte 1
MOSI
CTRL1
CTRL2
XFIFO
XFIFO
XFIFO
XFIFO
CTRL1
CTRL2
CTRL3
CTRL4
SCLK
Indeterminate State
ITD06310
a) Transfer of STA 1/ CTRL1 only CS
b) Transfer of STA 1, 2; CTRL1, 2 CS
MISO
STA1
MISO
STA 1
STA 2
MOSI
CTRL1
MOSI
CTRL1
CTRL 2
c) Transfer of CTRL3 and CTRL4 CS
MISO
STA1
STA 2
MOSI
CTRL1
CTRL 2
CTRL 3
CTRL 4
Indeterminate State
ITD06311
Figure 16 Examples of SCI-Transfers
Semiconductor Group 32
Functional Description
Figure 17 shows an example how the SmartLink-P is interfaced to a Siemens SAB C510 family of microcontrollers or a Motorola MC68HC05 microcontroller.
PORT SCLK SDO
CS SCLK SDI SDO INT MCLK RST RST
ITS06312
SAB C510 68HC11 68HC05
SDI INT
SmartLink-P
PSB 2197
XTAL1/EXTAL RST
TR/TE
Figure 17 Interfacing the SmartLink-P to a Siemens SAB C510x or Motorola Microprocessor Microprocessor Clock Output The microprocessor clock is provided by the MCLK-output. Four clock rates are provided by a programmable prescaler. These are 7.68 MHz, 3.84 MHz, 1.92 MHz, 0.96 MHz. Switching between the clock rates is based on the lowest frequency and realized without spikes. The value after reset is 3.84 MHz. The clock rate is changed after CS becomes inactive. Interrupt Output The interrupt output is an open drain output. The INT-line can be activated at any time. The interrupt output is masked while CS is active. Nevertheless, the interrupt request itself will only be cleared if STA1 or STA2 (in case of C/l-change) is read (2). If CS becomes active and STA1 is not read during this access, INT becomes active again after CS is turned high (1).
Semiconductor Group 33
Functional Description
INT-Request (Internal) INT
CS
SCLK
MISO
x STA1 (1) (2)
ITD06313
Figure 18 Interrupt Output Reset Logic The SmartLink in provides two reset outputs (RST, RST) if the undervoltage detection is active. An alternative mode selects RST as input while RST outputs the inverse of RST. The undervoltage detection is not active in this mode. Additionally, a watchdog timer is included which is started by a particular sequence. If it underruns, a reset signal is generated and some of the internal registers are reset. Undervoltage Detection During power-up, the reset output is active until the threshold voltage of VHH has been reached. After that, a period of tr is counted until the reset output becomes inactive. It stays inactive until the supply voltage drops below threshold level VHL. While the supply voltage is below the thresholds, the microcontroller clock MCLK is stopped and the MCLK-output remains low. If the supply voltage falls below threshold VHL, the clock is stopped immediately which may result in a shorter high period of the clock signal.
Semiconductor Group 34
Functional Description
For VHL and the hysteresis between VHL and VHH the following values are specified. Parameter min. Limit Values max. 4.4 230 V mV Unit
VHL
Hysteresis (VHH - VHL)
4.2 50
minimum period (tmin) for the undervoltage detection is at maximum 11 s. The delay (td) after threshold voltages have been passed is maximum 1 s. During power-up, the reset pulse may be extended due to the oscillator start until a stable 15.36-MHz clock is achieved. Figure 19 shows the undervoltage control timing.
tr has a value of 1792 periods of the internal 32-kHz clock which is equal to 56 ms. The
VHH VHL VDD
~ ~
t min
RST
~ ~ ~ ~
RST
td
tr
td
tr
MCLK
ITD06314
Figure 19 Undervoltage Control Timing
Semiconductor Group 35
Functional Description
Watchdog Timer The counter which is used for the reset generation can be used as watchdog timer. Once the power detection reset has been elapsed, the counter is disabled. It can be enabled as watchdog timer with the first `10' sequence of the WTC1- and WTC2-bits. Once enabled, the software has to program `01', `10' sequences into the WTC1-, WTC2-bits each within 56 ms. If the next sequence doesn't occur within this period, a reset pulse is generated at the reset output which has a width of 56 ms. The watchdog reset will only effect the CTRL3-register to reset the SDS-bits so that SDS and BCL become low. The watchdog timer will also reset the CTRL1-register (PW5-0 bits, PRE1, 0) and the LCRI-bit so that the PWO/Ring output becomes low.
RST
RST WTC1, 2 Watchdog Enabled '10' < 56 ms '01' < 56 ms '10' < 56 ms '01' 56 ms 56 ms
ITS06315
Figure 20 Watchdog Operation IOM(R)-Clocks Signals during Reset The undervoltage detection generates internally a short reset pulse which is used to reset the internal registers and to trigger the 56 ms counter. After the short internal pulse is released, the Upn-transceiver is reset. As a result, lOM-clocks are generated at the begin of the 56 ms external reset pulse and last for 11 lOM-frames (1.375 ms). After that, the lOM-clocks are stopped if the Upn-interface remains deactivated. Generation of lOM-clocks is started after the SPU-bit is set in CTRL4 or if an external device requests lOM-clocks by pulling the data upstream (DU) line low. They are also started if an activation of the Upn-interface is triggered by the line card or terminal repeater.
Semiconductor Group 36
Functional Description
RST
~ ~ ~ ~
FSC
~ ~
DU
INT
~ ~
HDLC X mit -Reset
STA 1 : CIC = 1 STA 2 : CI 0 = 0000
C/I = 1111 in Buffer
No further CIC R until IOM -Clocks are running
ITD06316
Figure 21 IOM(R)-Clocks Signals during Reset The ClC-bit in the STA1-register is set when the microcontroller reads the STA1-register for the first time because the Upn-transceiver outputs a `DR' indication when it is reset. The `DC' C/l-indication is stored in the C/l-buffer register. The software, after reading the STA1- and STA2-register will not get another ClC-status change unless the lOM-clocks are running. The value of the buffer register is transferred into the STA2-register only while lOM-clocks are running. If the SmartLink is configured for an external reset, the lOM-clocks remain running during the reset input is active. IOM-clocks will be stopped after the Upn-transceiver is reset following the end of the reset pulse.
Semiconductor Group 37
~ ~
Internal Reset
Functional Description
2.1.3.2 IOM(R)-2 Interface in TE-Mode The SmartLink-P supports the IOM-2 terminal mode. The interface consists of four lines: FSC, DCL, DD and DU. FSC transfers a frame start signal of which the rising edge indicates the start of an IOM-2 frame (8 kHz). The FSC-signal is generated by the receive DPLL which synchronizes it to the received Upn-frame. The DCL-signal is the clock signal to synchronize the data transfer on both data lines (768 kbit/s frequency is twice the transmission rate (1.536 MHz)). The first rising edge indicates the start of a bit while the second falling edge is used to latch the contents of the data lines. Additionally the BCL- and SDS-signals are provided to connect standard codecs to the SmartLink-P. The BCL (bit clock) provides a clock signal synchronous to the lOM-data at the same data rate. SDS provides a strobe signal which is active high during the B1- or B2- or IC1-channel. The length of the FSC-signal on the IOM-2 interface will be reduced to one DCL-period every eighth IOM-2 frame. A reduced FSC-signal is generated after a code violation has been received from the Upn-interface. IOM(R)-2 Driver The output driver of the DD- and DU-pins is open drain. The output drivers are active for the selected time-slot bits and remain tristate during the rest of the frame. IOM(R)-2 Frame Structure The principle frame structure of the IOM-2 terminal mode is shown in figure 22. The frame is composed of three channels.
Semiconductor Group
38
Functional Description
CH0 MR MX DU B1 B2 MON0 D CI0 IC1 IC2
CH1 MR MX MON1 CI1
CH2 BAC TAD
IOM R IOM
R
U pn U pn
IOM R IOM
R
Transceiver
IOM
R
STA 2
CTRL 3
IOM
R
U pn
Output only during TIC-Bus Access MR MX DD B1 B2 MON0 D CI0 IC1 IC2 MON1 CI1 MR MX S/G A/B
Upn Upn
IOM R IOM
R
Transceiver Upn
IOM
R
R
IOM
Upn IOM Used for Enabling the HDLC Transmitter (if programmed)
R
ITD06317
Figure 22 IOM(R)-2 Terminal Mode * Channel 0 contains 144 kbit/s of user and signaling data (2B + D) plus a MONITOR and command/indicate channel for control and programming of the layer-1 transceiver. * Channel 1 contains two 64-kbit/s intercommunication channels plus a MONITOR and command/indicate channel to program or transfer data to other IOM-2 devices. * Channel 2 is used for the TlC-bus access. Only the command/indicate bits are specified in this channel.
Semiconductor Group 39
Functional Description
IOM(R)-2 Time-Slots used by the SmartLink-P The SmartLink-P accesses a subset of all IOM-2 channels. It provides access to the D-channel, the C/l-channel 0 and to the TlC-bus. The information of the B1-, B2- and D-channel time-slots is forwarded transparently between the IOM-2 interface and the transceiver (in the activated state). Other time-slots (like IC1, IC2, MON0, MON1 with control/status bits) are not influenced by the SmartLink-P. They can be controlled by other devices connected to the IOM-2 interface. The most significant three bits of the C/l-channel 1 are received in the STA2-register. Command/Indicate 0 C/l-code changes occur at maximum rate of 250 s (2 x lOM-frames). During activation the following sequence could occur:
PU
RSY
AR
AI
2. Reg.
RSY
AR
AI
1. Reg.
PU
CS
PU STA 2
AI STA 2
ITD06318
If the software is not able to follow each change, it will at least get the first one and the last one. Thus it knows from where it started and about the current status. Stop/Go Bit The Stop/Go (S/G) bit can be controlled by the received Upn T-channel to transmit the state of the line card arbiter to the HDLC-controller of the terminal. If selected by the SGE-bit, the HDLC-transmitter evaluates the state of the S/G-bit before and during transmission of an HDLC-frame.
Semiconductor Group 40
Functional Description
Available/Busy Bit The AB-bit has been added to the IOM-2 frame for the operation of a S/T-terminal adapter based on the SBCX. Since the SmartLink is not capable of transferring monitor channel data, a masked version of the SBCX was defined which reaches all necessary modes after reset. This part is called PSB 20810. The terminal needs to know if a PSB 20810 is plugged in to switch the routing of the downstream T-channel correctly. MUTE Function The SDS-bits control the data path of the upstream B-channel information. B-channel information may either be transparent (IOM Upn) or disconnected. In the latter state, a constant value of all `1' is transmitted to the Upn-interface instead of the IOM-2 B-channel information. This feature can be used to realize a MUTE function together with a simple codec. The downstream B-channel data is not influenced. B-Channel Loopback The information of a B-channel (B1 or B2) received from the Upn-interface can be looped back to the Upn-interface. The selection is done via the SDS2-0 bits.
SDS2-0
(Mute) DU (Loopback)
1 U pn Transceiver B1 or B2
U pn
DD
ITS06319
Figure 23 B-Channel Manipulation
Semiconductor Group
41
Functional Description
2.1.3.3 Upn-Interface Figure 24 demonstrates the general principles of the Upn-interface communication scheme. A frame transmitted by the exchange (LC) is received by the terminal equipment (TE) after a line propagation delay. The terminal equipment waits the minimum guard time (5.2 s) while the line clears. It then transmits a frame to the exchange. The exchange will begin a transmission every 250 s (known as the burst repetition period). However, the time between the reception of a frame from the TE and the beginning of transmission of the next frame by the LC must be greater than the minimum guard time. Within a burst, the data rate is 384 kbit/s and the 38-bit frame structure is as shown in figure 24. The framing bit (LF) is always logical `1'. The frame also contains the user channels (2B + D). Note that the B-channels are scrambled. It can readily be seen that in the 250-s burst repetition period, 4 D-bits, 16 B1-bits and 16 B2-bits are transferred in each direction. This gives an effective full duplex data rate of 16 kbit/s for the D-channel and 64 kbit/s for each B-channel. The final bit of the frame is called the M-bit. Four successive M-bits, from four successive Upn-frames, constitute a superframe (figure 24). Three signals are carried in this superframe. The superframe is started by a code violation (CV). From this reference, bit 3 of the superframe is the service channel bit (S). The S-channel bit is transmitted once in each direction in every fourth burst repetition period. Hence the duplex S-channel has a data rate of 1 kbit/s. It conveys test loop control information from the LC to the TE and reports of transmission errors from the TE to the LC. Bit 2 and bit 4 of the superframe are the T-bits. Not allocated to a specific function until now (cf PEB 2095 IBC and PEB 20950 ISAC-P) they can be used for D-channel control in conjunction with PEB 20550 ELIC(R) and PEB 2096 OCTAT-P. In order to decrease DC-offset voltage on the line after transmission of a CV in the M-bit position, it is allowed to add a DC-balancing bit to the burst. The LC-side transmits this DC-balancing bit, when transmitting INFO 4 and when line characteristics indicate potential decrease in performance. Note that the guard time in TE is always defined with respect to the M-bit, whereas AMIcoding includes always all bits going in the same direction. The coding technique used on the Upn-interface is half-bauded AMI-code (i.e. with a 50 % pulse width). A logical `0' corresponds to a neutral level, a logical `1' is coded as alternate positive and negative pulses. In the terminal repeater mode, no DC-balancing bit will be generated. The loop length of the TR-mode is limited to 100 m.
Semiconductor Group
42
Functional Description
tr
LT, TR
TE
td
tg
td
LF 1
B1 8
B2 8
D 4 99 s
B1 8
B2 8
M DC 1
CV T S T
ITD05337
Binary Value Line Signal
0
1
0
0
1
1
0
1
0
1 +V 0 -V
CV.
ITD05338
Figure 24 Upn-Interface Structure Scrambler/Descrambler B-channel data on the Upn-interface is scrambled to give a flat continuous power density spectrum and to ensure enough pulses are present on the line for a reliable clock extraction to be performed at the downstream end. The SmartLink-P therefore contains a scrambler and descrambler, in the transmit and receive directions respectively. The basic form of these are illustrated in figure 25. The form is in accordance with the CCITT V.27 scrambler/descrambler and contains supervisory circuitry which ensures no periodic patterns appear on the line.
Semiconductor Group 43
Functional Description
D0 = Di + Ds ( Z -6 + Z -7 ) Scrambler OUT Ds
Z -1
Z -1
Z -1
Z -1
Z -1
Z -1 Ds Z -6
Z -1
Di Scrambler IN
+
Ds Z -6 + Ds Z -7
+
Ds Z -7
ITD05339
Do = Di = Ds (1 + Z -6 + Z -7 ) Descrambler IN Ds
Z -1
Z -1
Z -1
Z -1
Z -1
Z -1 Ds Z -6
Z -1
Do Descrambler OUT
+
Ds Z -6 + Ds Z -7
+
Ds Z -7
ITD05340
Figure 25 Scrambler/Descrambler Info Structure on the Upn-Interface The signals controlling the internal state machine on the Upn-interface are called infos. In effect these pass information regarding the status of the sending Upn-transceiver to the other end of the line. They are based upon the same format as the Upn-interface frames and their precise form is shown in table 1. When the line is deactivated info 0 is exchanged by the Upn-transceivers at either end of the line. Info 0 effectively means there is no signal sent on the line in either direction. When the line is activated info 3 upstream and info 4 downstream are continually exchanged. Both info 3 and info 4 are effectively normal Upn-interface data frames containing user data and exchanged in normal burst mode. Note that the structure of info 1 and info 2 are the same, they only differ in the direction of transmission. Similarily info 3/info 4 and info 1w/info 2w also constitute info pairs. This will be important when considering looped states. As we will see, the other infos are exchanged during various states which occur between activation and deactivation of the line.
Semiconductor Group 44
Functional Description
Table 1 Upn-Interface Info Signals Name Info 0 Info 1w Direction Upstream Downstream Upstream Description No signal on the line Asynchronous wake signal 2-kHz burst rate F0001000100010001000101010100010111111 Code violation in the framing bit 4-kHz burst signal F000100010001000100010101010001011111M1) DC2) Code violation in the framing bit 4-kHz burst signal F000100010001000100010101010001011111M1) DC2) Code violation in the framing bit 4-kHz burst signal No code violation in the framing bit User data in B-, D- and M-channels B-channels scrambled, DC-bit2) optional 4-kHz burst signal No code violation in the framing bit User data in B-, D- and M-channels B-channels scrambled, DC-bit2) optional
Info 1
Upstream
Info 2
Downstream
Info 3
Upstream
Info 4
Downstream
Note:
1)
The M-channel superframe is transparent: S-bits transparent (1-kbit/s channel) T-bits transparent (2-kbit/s channel) DC-balancing bit
2)
Semiconductor Group
45
Functional Description
The following test patterns are also included: Name Info T1 Direction Upstream Description Test signal single pulse 2-kHz burst rate 100000000... Test signal continuous pulses 192-kHz clock rate 111111111...
Info T2
Upstream
Upn-Transceiver Figure 26 depicts the transceiver architecture and the analog connections of the SmartLink-P. External to the line interface pins Lla and Llb a transformer and external resistors are connected as shown. Note that the internal resistors of the transformer are calculated as zero. The actual values of the external resistors must take into account the real resistor of the chosen transformer. The receiver section consists of an amplifier followed by a peak detector controlling the thresholds of the comparators. In conjunction with a digital oversampling technique the PSB 2197 SmartLink-P covers the electrical requirements of the Upn-interface for loop lengths of up to 4.5 kft on AWG 24 cable and 1.0 km on J-Y(ST) Y 2 x 2 x 0.6 cable.
Semiconductor Group
46
Functional Description
Transformer Ratio 2:1
U pn 25 2:1
175 100 nF SmartLink-P
PSB 2197
175 25
0.33 F
ITS06320
Transformer Ratio 1:1.25
U pn 29 1: 1.25
78 SmartLink-P 100 nF 0.33 F 78 29
ITS06321
PSB 2197
Figure 26 Upn-Transceiver of the SmartLink-P Upn-Transceiver Timing The receive PLL uses the 15.36-MHz clock to generate an internal 384-kHz signal which is used to synchronize the PLL to the received Upn-frame. The PLL outputs the FSCsignal as well as the 1.536-MHz double bit clock signal and the 768-kHz bit clock. The length of the FSC-signal is reduced in the next IOM-2 frame which is started while a Upn-frame is received, after a code violation has been detected. The reduced length of the FSC-signal provides synchronization between the TE- and the TR-transceiver to gain the shortest delays on the Upn T-channel data forwarding.
Semiconductor Group 47
Functional Description
D U pn B1 B2 B1 B2
CV B1 B2
D B1 B2
CV B1 B2
D B1 B2
T B1 B2
D B1 B2
T
FSC
DU
B1 B2
B1 B2
D DD
B1 B2 B1 B2
D
BAC
D
D
S/G
ITD05348
Figure 27 Upn-Transceiver Timing B1-, B2-Channels The lOM-interface B-channels are used to convey the two 64-kbit/s user channels in both directions. However, the PSB 2197 SmartLink-P only transfers the data transparently in the activated state (incl. analog loop activated) while the data are set to `1' in any non activated state (cf. state descriptions). D-Channel Similar to the B-channels the layer-1 (Upn) part of the PSB 2197 SmartLink-P transfers the D-channel transparently in both directions in the activated state. T-Bit Transfer In TE-mode the layer-1 (Upn) part of the PSB 2197 SmartLink-P conveys the T-bit position of the Upn-interface to either the S/G-bit position or the A/B-bit position according to the register programming. The exact bit polarities are as follows: Downstream (Upn IOM(R)) T-to A/B-mapping (CTRL3: TCM = 1): T = 0: T = 1: T = 0: T = 1:
Semiconductor Group
A/B = 0 S/G = 1 blocked A/B = 1 S/G = 1 available A/B = 1 S/G = 1 blocked A/B = 1 S/G = 0 available
48
T-to S/G-mapping (CTRL3: TCM = 0):
Functional Description
Upstream (IOM(R) Upn) The T-channel in upstream direction is controlled by the BAC-bit of the IOM-2 interface. The T-channel transmits the inverse of the BAC-bit. Special care is taken so that the slave terminal will only send one HDLC-frame until the TlC-bus of the master IOM-2 interface is release. This is achieved by a circuitry which latches the BAC-state of `1' until at least one T-bit has been transmitted with the value of `0' which releases the TlC-bus of the master IOM-2 interface. BAC to T-mapping: BAC = 1 BAC = 0 Control of the Upn-Transceiver An incorporated finite state machine controls the activation/deactivation procedures and communications with the layer-2 section via the lOM-Command/Indicate (Cl) channel 0. Diagnostics Functions Two test loops allow the local or the remote test of the transceiver function. Test loop 3 is a local loop which loops the transmit data of the transmitter to its receiver. The information of the IOM-2 upstream B- and D-channels is looped back to the downstream B- and D-channels. The M-bit is also transparent which means that the state of the BAC-bit is looped back to the S/G- or AB-bit. Test loop 2 is activated by the Upn-interface and loops the received data back to the Upn-interface. The D-channel information received from the line card is transparently forwarded to the downstream IOM-2 D-channel. The downstream B-channel information on IOM-2 is fixed to `FF'H while test loop 2 is active. T=0 T=1 no D-channel request D-channel request
Semiconductor Group
49
Functional Description
2.1.4
D-Channel-Arbitration in TE-Mode
The SmartLink-P supports different kinds of D-channel arbitration in order to share the upstream D-channel by several communication controllers and to allocate the D-channel from the Upn-interface. The following functions are performed depending on the register settings: - Allocation of the upstream D-channel bits on the IOM-2 interface via the TlC-bus. - Control of the HDLC-transmitter by the stop/go bit. TlC-Bus Access The terminal IC-bus provides an access mechanism to share the D-channel in upstream direction by several communication controllers (ICC, ISAC, SmartLink) connected to one layer-1 device. The Bus Accessed bit (BAC) is used to indicate that the TlC-bus is currently occupied and other devices have to wait. The different communication controllers use individual TlC-bus addresses in the range of `0' to `7'. A collision detection mechanism checks each bit of the TIC-bus address for congestion. Since a `0' has higher priority against a `1', a TlC-bus address of `0' has the highest priority and `7' has the lowest one. TlC-Bus Access Mechanism During idle state, the Bus Accessed bit (BAC) is set to `1' and the TlC Bus Address (TBA) is `7'. If a communication controller needs access to the D-channel bits, it will check the state of the BAC bit. If BAC is `1' (idle) it will place its TlC-bus address on the TAD2-0 bits. After each bit has been outputted, it checks for collision and stops transmitting if a collision is detected (`1' transmitted, `0' detected on the DU-line). If the TlC-bus address has been transmitted successfully, the D-channel and C/I-channel 0 are controlled from the controller in the next frame and the BAC-bit is set to `0'. After the TlC-bus access is completed, the TlC-bus returns to the idle state (BAC = `1', TAD = `111') and other devices can gain access. A device which has detected a collision during the transmission of the TlC-bus address will restart after the BAC-bit becomes idle `1' again. In order to provide access to all controllers, the device which has gained successful access to the TlC-bus will wait for two idle frames before it starts another access. Note: The SmartLink will also set the BAC-bit if the TlC-bus address of seven (`111') is programmed. This is different to the TlC-bus operation of the ICC (PEB 2070) and ICC-based devices (ISAC-S (TE), ISAC-P (TE)). Stop/Go Bit The stop/go bit controls the transmitter output of the D-channel HDLC-controller if selected by the SGE-bit. The transmitter is active, as long as the stop/go bit indicates go (`0').
Semiconductor Group 50
Functional Description
The S/G-bit is checked before a HDLC-frame is started and monitored during the transmission of the HDLC-frame. The HDLC-transmitter aborts the transmission of an HDLC-frame if the S/G-bit becomes `Stop' after the begin of a frame was transmitted. It will output `11' in the D-bits of the lOM-frame beginning with the following lOM-frame after S/G becomes `Stop' until `Go' is indicated. The evaluation of the S/G-bit must be enabled by the CTRL3:SGE-bit. The stop/go bit can be controlled by the downstream T-bit which indicates the receive capability of the line card or by the PSB 20810 in case a S/T-interface adapter is plugged onto the IOM-2 interface. HDLC-Controller Access Modes The access mode of the D-channel HDLC-controller is programmable. It can ignore the TlC-bus, use the TlC-bus to gain access and evaluate the S/G-bit. Table 2 shows the possible combinations. Table 2 HDLC-Controller Access Modes TBU SGE TIC-Bus Access S/GEvaluation 1 1 0 0 0 1 0 1 Yes Yes No No No Yes No Yes Application TIC-bus access without S/G-bit evaluation TIC-bus access with S/G-bit evaluation Permanent D-channel access without S/G-bit evaluation Permanent D-channel access with S/G-bit evaluation
If the HDLC-controller is set to a mode where the S/G-bit is evaluated, the transmission is started if the S/G-bit becomes go (`0') and stopped if the S/G-bit becomes stop (`1'). If the D-channel becomes not available before the final bit of the closing flag has been sent, the transmission is aborted. In case the collision occurred during the first XFIFO contents, the frame is automatically retransmitted. If the first XFIFO contents has already been sent, a XMR-status is generated and the microcontroller has to repeat the complete frame again.
Semiconductor Group
51
Functional Description
2.1.5 - - - - -
HDLC-Controller
The HDLC-controller performs the layer-2 functions of the D-channel protocol: Flag generation/detection Zero bit insertion/deletion CRC-generation/check (CCITT polynomial X16 + X12 + X6 + 1) Abort generation Idle signal generation (`1')
HDLC-Frame Formatting The HDLC-transmitter starts a HDLC-frame with a flag. It continues with the data of the XFIFO. The end of a frame is indicated by a closing flag preceeded by the 16-bit CRC-check sum or by an abort sequence.
Flag
Data
CRC
Flag
XFIFO Figure 28 HDLC-Transmitter Format The HDLC-receiver hunts for flags which are not followed by another flag or an abort sequence. It stores the information in the RFIFO until the end of the frame has been detected. The status of the received frame (CRC-status, end of frame condition etc.) is reported via a status byte which is stored in the RFIFO immediately following the last byte of a message. The HDLC-receiver of the SmartLink will receive two frames correctly if they are separated by only one common flag (shared flag). It will also receive two frames correctly if they are separated by two flags (back-to-back frames).
Flag
Data
CRC
Flag
Data
RSTA
RFIFO Figure 29 HDLC-Receiver Format
Semiconductor Group 52
Functional Description
2.1.6
Terminal Specific Functions
2.1.6.1 LCD-Contrast Control The Pulse Width Output/Ring provides a pulse width modulated signal which can be varied in 14 linear steps between OFF and ON. The repetition frequency is 8.5 kHz. The LCD-contrast control is enabled by setting the LCRI-bit to `0'. The output of the PWM is filtered by a low pass filter and transformed to the required voltage range by an external transistor as shown in figure 30.
V DD
PWO SmartLink-P
LCD Contrast
PSB 2197
- V LCD
117.6 s
ITS06322
Figure 30 LCD-Contrast Control
Semiconductor Group 53
Functional Description
2.1.6.2 Ring Tone Generation The SmartLink-P can generate frequencies at the Pulse Width Output/Ring. The ring tone generator uses a 16 kHz-clock input and divides it by a programmable value of n = 1 to 63. The PWO/Ring output is tristate while PW5-0 are `000000'. The following list shows examples of frequencies: Value 8 10 11 12 14 15 17 19 20 21 23 27 29 33 36 41 51 (PW5-0) (001000) (001010) (001011) (001100) (001110) (001111) (010001) (010011) (010100) (010101) (010111) (011011) (011101) (010001) (100100) (101001) (110011) Frequency (Hz) 2000 1600 1454 1333 1142 1066 941 842 800 761 695 592 551 484 444 390 313
Ring tones change or stop at the end of a half or full cycle. This includes switching to tristate.
Semiconductor Group
54
Functional Description
PWO/RING SmartLink-P
Piezo
PSB 2197
16 kHz
:(n+1) n = 1...63
PWO/ RING
250...8000 Hz
ITS06323
Figure 31 Ring Tone Generation
Semiconductor Group
55
Functional Description
2.2 2.2.1
Terminal Repeater (TR) Mode General Functions and Device Architecture (TR-Mode)
In TR-mode the following functions are provided: * Upn-interface transceiver, functionally fully compatible to both PEB 2095 IBC and PEB 2096 OCTAT-P, also features the terminal repeater mode * IOM-2 interface for terminal application * A microcontroller clock is not generated
TR-Mode
15.36 MHz 100 ppm 0V + 5V
U pn LI a
XTAL2
XTAL1
VSS
VDD
DD DU
IOM -2
R
LI b
FSC DCL
TR/TE ( +5 V ) PWO/RING/MODE ( +5 V ) VDDDET/TCM RST RST SCLK MOSI CS
VSS
VSS
VDD
ITS06324
Figure 32 Device Architecture in TR-Mode
Semiconductor Group 56
Functional Description
2.2.2
Clock Generation (TR-Mode)
In TR-mode, the oscillator is used to generate a 15.36-MHz clock signal. This signal is used by the DPLL to synchronize Upn-frames to the received IOM-2 clocks (FSC, DCL). No other clocks are generated.
DU DD
U pn - State Machine
D - Channel Arbitration
TIC - Bus Controller (CIO)
IOM R -2 Interface
15.36 MHz
OSC
15.36 MHz
FSC DPLL DCL
ITS05355
Figure 33 Clock Generation in TR-Mode
Semiconductor Group
57
Functional Description
2.2.3
Interfaces (TR-Mode)
In TR-mode, two interfaces are active: * IOM-2 interface: as a universal backplane for terminals * Upn-interface towards the two-wire slave subscriber line The microcontroller interface remains active in TR-mode. As a result, the CS-input has to be connected to VDD and MOSI has to be connected to VSS avoid accidental programming. 2.2.3.1 IOM(R)-2 Interface in TR-Mode The SmartLink-P supports the IOM-2 terminal mode. The interface consists of four lines: FSC, DCL, DD and DU. FSC and DCL provide the clock inputs to synchronize the Upn-transceiver to the IOM-2 interface. DU and DD are open drain outputs.
CH0 MR MX DU B1 B2 MON0 D CI0 IC1 IC2
CH1 MR MX MON1 CI1
CH2 BAC TAD
**
U pn U pn
**
IOM
R R
IOM R IOM
R
Transceiver U pn
IOM
Indicates Activated State of Upn Interface
'O' Indicates Presents of TR
'011'
IOM
R
* Output only during TIC-Bus Access
MR MX DD B1 B2 MON0 D CI0 IC1 IC2 MON1 CI1 MR MX S/G A/B
IOM R IOM
R
U pn U pn
IOM R IOM
R
Transceiver
U pn
Used to Control the T-Channel
ITD05356
Figure 34 IOM(R)-2 Frame Structure in TR-Mode
Semiconductor Group 58
Functional Description
The SmartLink-P transfers the B-channel information between the IOM-2 and the Upn-interface during the activated state. During all other states, `FF' is output. The C/l-channel 0 as well as the upstream D-bits are occupied by the TR-SmartLink after a TlC-bus access has been performed. The BAC- and TAD-bits are used for the TlC-bus access. The SmartLink-P in TR-mode pulls bit 5 of the upstream command/indicate channel 1 to `0' after reset and remains `0' for identification of the TR-module by a terminal SmartLink-P or ISAC-P TE. Bit 6 of the upstream C/l-channel 1 is also controlled by the SmartLink-P in TR-mode. It is set to `0' if the Upn-interface is in the activated state. Otherwise, the bit remains `1'. 2.2.3.2 Upn-lnterface in TR-Mode Upn-Transceiver The transmitter uses the received FSC-signal to start the generation of a Upn-frame. If a short FSC-length (1 x DCL) is detected, the superframe counter is reset and the next Upn-frame will transmit the CV in the M-bit. During normal length of the FSC-signal (64 DCL-clocks), the superframe counter is not changed.
FSC D DU B1 B2 D DD B1 B2
B1 B2
BAC
B1 B2
D
B1 B2
D
B1 B2
D
D
B1 B2
D
S/G
B1 B2
D
U pn
B1 B2
B1 B2 T
B1 B2
B1 B2 CV
B1 B2
B1 B2 CV
B1 B2
B1 B2 T
ITD05357
D Upstream
D Downstream
D Upstream
D Downstream
Figure 35 Upn-Transceiver Timing
Semiconductor Group 59
Functional Description
Control of the Upn-Transceiver An incorporated finite state machine controls the activation/deactivation procedures and communications with the layer-2 section via the lOM-Command/Indicate (C/l) channel 0. In TR-mode, activation from the terminal side is started by a power-up sequence in case the FSC- and DCL-clocks are turned off. After that, a TlC-bus access is performed and activation is started by outputting the C/l-code `AR'. After that, the Upn-interface is activated and after completion of the procedure, the C/l-code `Al' is output. The length of the FSC-signal is monitored. The state-machine of the Upn-transceiver is reset every time, a FSC-period of less than 96 bits is detected. It will generate a reset signal for the state machine which is active for 6 lOM-frames. As a result, 4 or 5 info 0 frames will be transmitted on Upn a to force the TE-device in the level detect (resynchronization) state. This number of info 0 frames is still less than is required to detect Info 0 by the TE-device (2 ms, 8 info 0 frames). This procedure is necessary to avoid incorrect switching of internal B-channel buffers which corrupt the sequence of B-channel transfer between IOM and Upn. 2.2.4 D-Channel-Arbitration in TR-Mode
The D-channel arbitration is done using the TlC-bus features and the T-channel of the Upn-interface. TlC-Bus Idle If the TlC-bus is idle (BAC = `1', TAD = `111'), upstream D-channel data is transparently switched to the IOM-2 D-channel. No C/l0-code is transmitted by the TR-SmartLink. D-Channel Request A D-channel request is indicated by the terminal connected to the TR-SmartLink by setting the upstream T-channel to `1' (inverse of its IOM-2 BAC-bit). As a result, the TR-SmartLink tries to access the TlC-bus by outputting the TIC-bus address (`011'). After successful transmission of all three bits, the BAC-bit is set to `1' in the following IOM-2 frame and the TlC-bus is occupied. On the C/l-channel 0, the code `Al' (`1100') is output. D-Channel Release After the terminal connected to the TR-SmartLink has completed its HDLC-frame, the upstream T-channel becomes `0' (inverse of its IOM-2 BAC-bit). This transition from T = `1' to T = `0' is delayed by the TR-SmartLink by two lOM-frames before the TlC-bus is released. This delay is necessary to assure that the D-channel contents of the Upnframe which included the T-channel is output completely.
Semiconductor Group
60
Semiconductor Group
0 0 xx 0 01 0 11 0 11 0 10 0 01 0 11 0 11 1 10 1 xx 1 TAD xx 0 xx01 CV T 0 11 0 11 0 10 1 01 0 11 0 11 0 10 S T 0 xx 1111 T 1001 S 1111 T CV 0 xx 0 xx 10xx CV T 0 xx 0 xx 0 T
ITD06326
FSC
Figure 36 D-Channel Arbitration in TR-Mode
Master-DU
Master-DD
61
CV
Slave-DU
xx
0 01
Functional Description
Slave-DD
Functional Description
2.2.5
Reset
In TR-mode, the undervoltage detection is not active. To reset the SmartLink-P in TR-mode an external reset signal must be applied on the RST input. The reset will deactivate the Upn-transceiver and it will abort any TIC-bus access currently in progress. The TIC-bus returns to idle. While the reset signal is active, at least 40 clock pulses must be applied to XTAL1 and at least 4 DCL-pulses. More than 10 clock pulses on XTAL1 are required after reset becomes inactive. At least 6 IOM-frames are necessary after reset is released to put the Upn-transceiver in its deactivated state from which an asynchronous awake is possible if a level is detected on the Upn-interface pins.
RST
XTAL 1
_ < 40 Clocks _ < 10 Clocks
FSC
DCL
_ < 4 DCL _ < 6 IOM -Frames
R
U pn Reset
U pn deactivated Software Awake possible
ITD06327
Figure 37
Semiconductor Group 62
Functional Description
2.3 2.3.1
HDLC-Controller Mode General Functions and Device Architecture (HDLC-Controller Mode)
Figure 38 depicts the detailed architecture of the PSB 2197 SmartLink-P in HDLCcontroller mode: * * * * Serial control port HDLC-controller with 2 x 4 byte FlFOs per direction TlC-bus access control IOM-2 interface for terminal application
DU DD FSC DCL BCL SDS
IOM -2 Interface
R
TIC- Bus
HDLC Transmitter
HDLC Receiver
CIO
XTAL 1 TR/TE PWO/RING/MODE
Clock
1)
VDD VDD
VDDDET
Serial Control Port
Reset Logic
VDDDET/TCM
SCLK MOSI MISO CS
INT
RST RST
ITS06328
Figure 38 Device Architecture of the SmartLink-P in HDLC-Controller Mode
Semiconductor Group 63
Functional Description
2.3.2
Clock Generation (HDLC-Controller Mode)
In HDLC-controller mode, the oscillator input is used to achieve the reset state of the Upn-transceiver. All other functions which use the oscillator frequency in TE-mode (undervoltage detection, watchdog, microcontroller clock output, PWO/RING) are disabled. The IOM-2 clock signals (FSC, DCL) are used to synchronize the HDLC-data transfer and the access to the TIC-bus. A bit clock signal as well as a strobe signal for B1, B2 or IC1 may be generated.
DU DD
HDLC Controller
TIC-Bus Controller (CIO)
IOM -2 Interface
R
SDS BCL
FSC DCL
ITS06329
Figure 39 Clock Generation in HDLC-Controller Mode 2.3.3 Interfaces (HDLC-Controller Mode)
The PSB 2197 SmartLink-P serves two interfaces in HDLC-controller mode: * Serial microcontroller interface for higher layer functions * IOM-2 interface: between layer-1 and layer-2 and as a universal backplane for terminals * Bit clock and strobe signal generation 2.3.3.1 Microcontroller Interface The SmartLink-P provides a serial microcontroller interface which is compatible to the SPI-interface of Motorola or Siemens C510x microcontrollers. Its function is identical to the TE-mode.
Semiconductor Group 64
Functional Description
2.3.3.2 IOM(R)-2 Interface in HDLC-Controller Mode The SmartLink-P supports the IOM-2 terminal mode. The interface consists of four lines: FSC, DCL, DD and DU. FSC and DCL provide the clock inputs to synchronize the data transfer over the IOM-2 interface. DU and DD are open drain outputs. A bit clock and strobe signal may be generated locally.
CH0 MR MX DU B1 B2 MON0 D CI0 IC1 IC2
CH1 MR MX MON1 CI1
CH2 BAC TAD
IOM R IOM
R
Transceiver
CTRL 1:2-0
IOM
R
STA 2 CTRL 3
IOM
R
U pn
Output only during TIC-Bus Access MR MX DD B1 B2 MON0 D CI0 IC1 IC2 MON1 CI1 MR MX S/G A/B
Transceiver Upn
IOM
R
R
IOM
Used for Enabling the HDLC Transmitter (if programmed)
ITD06330
Figure 40 IOM(R)-2 Frame Structure in HDLC-Controller Mode The C/l-channel 0 as well as the upstream D-bits are occupied by the HDLC-controller mode SmartLink after a TlC-bus access has been performed. The BAC- and TAD-bits are used for the TlC-bus access. The SmartLink-P in HDLC-controller mode outputs the value of CTRL1:2-0 as Cl1 bits 7 to 5. After reset, they remain `1'. All other time-slots are not influenced by the SmartLink-P in HDLC-controller mode.
Semiconductor Group 65
Functional Description
2.3.4
D-Channel-Arbitration in HDLC-Controller Mode
The D-channel arbitration is identical to the one in TE-mode. 2.3.5 HDLC-Controller
The HDLC-controller functions are identical to the ones in TE-mode. 2.3.6 Reset
The HDLC-controller mode is reset by applying a reset pulse to the RST-input. To bring the Upn-transceiver to a low power state, the following requirements must be fulfilled: While reset is active, at least 40 clock pulses must be applied to XTAL1. After reset is released, another 10 clock pulses are required. The Upn-transceiver enters its low power deactivated state after 6 lOM-frames which are generated after the 50 clock pulses on XTAL1 have elapsed.
RST
XTAL1 < 40 Clocks
_ < 10 Clocks
FSC
DCL
_ < 6 IOM R -Frames
U pn Reset
U pn Deactivated
ITD06331
Figure 41 Reset
Semiconductor Group 66
Operational Description
3 3.1 3.1.1
Operational Description TE-Mode Interrupt Structure and Logic
The SmartLink-P provides one interrupt output which is used to indicate a change in the receiver or transmitter status or a change in the CI0-code. The microcontroller has to read the first status byte (STA1). The first status byte indicates changes of the receiver/transmitter section. CI0-code changes are indicated by the ClC-bit. In case of a CI0-change, the microcontroller has to evaluate the second status byte (STA2). It contains the new CI0-code value. Reading the STA1-status byte clears the interrupt request and the RPF-, RME-, XFS-, RFO-bits. The ClC-status bit and the interrupt generation by that bit is cleared by reading STA2.
INT
And/Or
CTRL2
RIE
ISYNC
RPF
RME
XFS1
XFS0
RFO
CIC
RBC1
RBC0
STA1
CI1/7
CI1/6
CI1/5
XFW
CI0
CI0
CI0
CI0
ITS06332
STA2
Figure 42 SmartLink-P Interrupt Structure The transmitter and C/l-change interrupts are permanently enabled. The generation of receiver interrupts is enabled by the RlE-bit. After reset, this bit is cleared and receiver interrupts are disabled. Changes in the received CI1-bits as well as a change in the XFW-bit will never generate an interrupt.
Semiconductor Group 67
Operational Description
3.1.2
Control of the Upn-Transceiver
3.1.2.1 Power-Down of the IOM(R)-2 Interface In order to reduce power consumption in the non-operational status the IOM-2 interface is brought into power down while the Upn-transceiver is in the deactivated state. The clocks are stopped at bit position 30 (starting with 1). FSC remains high, DCL remains at low voltage level, the data lines remaining pulled up by the external pull up resistors. For the exact procedures please refer to the IOM-2 Reference Guide Edition 3.91. Since the length of the FSC-signal is reduced every eight frames, the oscillator stops only during the regular length of a FSC-signal. BCL and SDS if enabled remain `0' during power-down. During power-down state (C/l = `1111'), only the lOM-clock signals are turned off. The oscillator, the Upn-awake detector is active as well as the microcontroller clock, pulse width modulator clock and watchdog counter. The power-down state is left when an asynchronous awake signal has been detected. The IOM-clocks are started. After the asynchronous awake signal is stopped, one device on IOM-2 must output CI0-codes different from `DI' (Deactivation Indication, `1111') to keep the IOM-2 interface running. The asynchronous awake may be generated by any device by pulling the DU-line to `0'. The SmartLink in TE-and HDLC-controller mode can force DU to `0' by setting the SPU-bit in CTRL4. 3.1.2.2 Activation/Deactivation of the Upn-lnterface The Upn-transceiver functions are controlled by commands issued in the CTRL4register. These commands are transmitted over the C/l-channel 0 and trigger certain procedures such as activation/deactivation and switching of test loops. Indications from layer-1 are obtained by evaluating the second status byte (STA2) after a ClC-status is indicated (STA1).
Semiconductor Group
68
Operational Description
3.1.2.3 Layer-1 Command/lndication Codes in TE-Mode Command (Upstream) Timing Reset Send Single Pulses Send Continuous Pulses Activate Request Activate Request Loop 3 Deactivation Indication Abbr. TIM RES SSP SCP AR ARL Dl Code 0000 0001 0010 0011 1000 1001 1111 Local analog loop Remarks Layer-2 device requires clocks to be activated Software reset Ones (AMI) pulses transmitted at 4 kHz Ones (AMI) pulses transmitted continuously
Indication (Downstream) Deactivation Request Power-Up Test Mode Acknowledge Resynchronization Activation Request Activation Request Loop 3 Activation Request Loop 2 Activation Indication
Abbr. DR PU TMA RSY AR ARL ARL2 AI
Code 0000 0111 0010 0100 1000 1001 1010 1100 1101 1110 1111
Remarks
Acknowledge for both SSP and SCP Receiver not synchronous Receiver synchronized Local loop synchronized Remote loop synchronized
Activation Indication Loop 3 AIL Activation Indication Loop 2 AIL2 Deactivation Confirmation DC
Local loop activated Remote loop activated Line and lOM-interface are powered down
Semiconductor Group
69
Operational Description
3.1.2.4 State Diagrams Activation/Deactivation The internal finite state machine of the PSB 2197 SmartLink-P controls the activation/deactivation procedures. Such actions can be initiated by signals on the Upn-transmission line (INFO's) or by control (C/l) codes sent over the C/I-channel 0 of the lOM-interface. The exchange of control information in the C/I-channel is state oriented. This means that a code in the C/l-channel is repeated in every lOM-frame until a change is necessary. A new code must be recognized in two consecutive IOM-frames to be considered valid (double last look criterion). The activation/deactivation procedures implemented by the PSB 2197 SmartLink-P agree with the Upn-interface as it is implemented by the PSB 2196 ISAC-P TE. In the state diagrams a notation is employed which explicitly specifies the inputs and outputs on the Upn-interface and in the C/I-channel 0. 3.1.2.5 TE-Mode State Description Reset, Pending Deactivation State after reset or deactivation from the Upn-interface by info 0. Note that no activation from the terminal side is possible starting from this state. A `DI'-command has to be issued to enter the state deactivated. Deactivated The Upn-interface is deactivated and the IOM-2 interface is or will be deactivated. Activation is possible from the Upn-interface and from the IOM-2 interface. Power-Up The Upn-interface is deactivated and the IOM-2 interface is activated, i.e. the clocks are running. Pending Activation Upon the command Activation Request (AR) the PSB 2197 SmartLink-P transmits the 2-kHz info 1w towards the network, waiting for info 2. Level Detect, Resynchronization During the first period of receiving info 2 or under severe disturbances on the line the Upn-receiver recognizes the receipt of a signal but is not (yet) synchronized.
Semiconductor Group
70
Operational Description
Synchronized The Upn-receiver is synchronized and detects info 2. It continues the activation procedure by transmission of info 1. Activated The Upn-receiver is synchronized and detects info 4. It concludes the activation procedure by transmission of info 3. All user channels are now conveyed transparently. Analog Loop 3 Pending Upon the C/l-command Activation Request Loop (ARL) the PSB 2197 SmartLink-P loops back the transmitter to the receiver and activates by transmission of info 1. The receiver is not yet synchronized. Analog Loop 3 Synchronized After synchronization the transmitter continues by transmitting info 3. Analog Loop 3 Activated After recognition of the looped back info 3 the channels are looped back transparently. Test Mode Acknowledge After entering test mode initiated by SCP-, SSP-commands.
Semiconductor Group
71
Operational Description
DC ARL
DI TIM
DI TIM
SCP TMA SSP Test Mode i it i
Deactivated i0 AR i0 i0
*
ARL Loop 3
DI TIM
SCP SSP
AR
PU
AR
Pending Activation i1w i0 DI AR i0
DI TIM
DI AR
PU
TIM
Power-Up i0 i0 i0
RSY
Level Detect i0 i0 i2 AR + DI ARL2 AR Synchronized i0 i1 i4 DI AI + AIL2 i2 DI AR i4 i0 DR AR TIM U pn ix IOM
R
i0
i2 x i4 x i0
DR DI i0
RES TIM
Reset
*
i2 RST RES OUT IN
Ind.
Cmd.
Activated i3 i4
Pending Deactivation i0 i0
State ir
Unconditional transitions initiated by commands: RES, SSP, SCP External pin: RST + : AR, AI indications if S = 0 ; ARL2, AIL2 indications if S = 1 (analog Loop 2)
ITD05369
Figure 43 State Diagram TE-Mode
Semiconductor Group 72
Operational Description
ARL
RES AR TIM DI PU ARL Pend. Loop 3 i1 i2 RES AR TIM DI ARL ARL i2 x i4 Loop 3 Synchroni. i3 i4 RES AR TIM DI AIL ARL i4 U pn ix IOM
R
i0
i2 OUT IN
Ind.
Cmd.
Loop 3 Activated i3 i4
State ir
ITD05370
Figure 44 State Diagram TE-Mode (Test Loop 3)
Semiconductor Group 73
Operational Description
3.1.2.6 Example of the Activation/Deactivation Figure 45 shows the activation/deactivation procedure between the line card (Octat-P) and the terminal (SmartLink-P).
TE PowerDown DC DI INFO 0
LC DC DI Deactivated State
~ ~
SPU = 1 PU AR, SPU = 0
~ ~
~ ~
~ ~
INFO 1w INFO 2 T1 RSY AR T3 AI T2 INFO 0 INFO 1 INFO 4 INFO 3 T3 AI Activated State T2 RDS T1 AR
~ ~
T4
~ ~
INFO 0 INFO 0
~ ~
~ ~
DR T4 DC
DR DC DI
INFO 0
DI
Deactivated State
IOM -2
R
U pn Interface
IOM -2
R
ITD05371
Figure 45 Activation/Deactivation (LC, TE)
Semiconductor Group 74
Operational Description
3.1.3
Operation of the Serial Control Interface
A state machine controls the operation of the serial control port. It performs the necessary read and write operations to the internal registers. Begin of Transmission The begin of a transmission is indicated by pulling CS low. This will force the MlSO-output to drive the current value of the shift register output. At the same time, the execution of HDLC-controller commands is disabled. The first falling edge will force the state machine to load the current value of STA1 into the shift register and output the MSB. The following clocks shift the contents of STA1 over the MlSO-line. At the same time, the MOSI-line receives the value of CTRL1. Its value is stored in the CTRL1-register with the rising edge of the last clock period. The state machine will transfer the contents of STA2 into the shift register at the next falling edge on the clock line and outputs the MSB of the shift register. The next clock pulses transfer the STA2-value while CLTR2 is received. The rising edge of the eighth clock period is used to transfer the contents of the shift register into CTRL2-register. The command bits are disabled until the end of the transfer. In transmit direction (SmartLink-P P), the contents of RFlFO-data will follow if a receive status condition was reported and receiver command has not been issued. Similar to register accesses, this occurs with the first falling edge of the clock signal. In receive direction (P SmartLink-P), the operation of the state machine depends on the value of XBC1, 0 and HXC1, 0 bits. If HXC1, 0 indicates a XTF or XTF x XME-command, the number of bytes indicated in XBC1, 0 are received and transferred into the XFIFO with the rising edge of every eighth clock signal. If HXC1, 0 indicates no command (`00') and XBC1, 0 indicates `01', the following two bytes are stored in CTRL3 and CTRL4 with the rising edge of every eighth clock signal. RFlFO-data is not output if CTRL2 indicates that CTRL3 and CTRL4 will follow. All further information will be ignored. End of Transfer At the end of the transfer which is determined by the CS-line to become high, the commands (XTF, XTF x XME, XRES, RMC, RMD, RRES) are enabled again.
Semiconductor Group
75
Operational Description
Error Detection The state machine monitors the number of bits transferred. Only if eight bits have been transmitted, the contents of the shift register is transferred into the proper register. No special error indication is provided. In order to avoid locking of the HDLC-operation by a spurious clock pulse on the serial control interface, two additional status bits are added. RFO (Receive Frame Overflow) indicates that the start of a frame could not be stored in the RFIFO. This indication is helpful if the value of the STA1-byte has been changed so that the RPF- or RME-status bit was not transferred correctly. The microcontroller has to acknowledge the RFIFO by RMC-commands until all frames which were buffered in the RFIFO have been read. XFW (Transmit FIFO Write Enable) informs that the XFIFO is free and data can be entered. In case a XPR-status bit is not transferred correctly over the serial control interface, the microcontroller may poll the XFW-bit after a certain period of time to see if the XFIFO is accessible. Timing between Bytes The bytes can follow immediately or with gaps between the bytes. There is no maximum pause specified. The only requirement is that the CS-Iine remains active during the gap. Minimum Pause between Accesses A minimum time of 10 DCL clocks must elapse between two accesses to the serial control interface (CS becoming low) to assure that a previously entered command is executed correctly.
Semiconductor Group
76
Operational Description
3.1.4
Control of the HDLC-Data Transfer
The control of the HDLC-data transfer is optimized for full duplex operation via the serial control interface. A standard interrupt response takes up to six bytes to read/write the HDLC FlFOs. 3.1.4.1 HDLC-Transmitter The HDLC-transmitter consists of a 2 x 4 byte FIFO. One half is connected with the transmit shift register while the other half is accessible via the microcontroller interface. Two status bits are controlled by the HDLC-transmitter to indicate a new status. The HDLC-transmitter is controlled by two bits which act as command. The corresponding bits of the CTRL2-register start the command. After the command has been executed, these bits are reseted automatically. One command is used to indicate that the contents of the XFIFO is part of a frame and has to be transmitted (XTF). Another command (XTF x XME) indicates that the final part of a message has been entered into the XFIFO and has to be transmitted. In this case, the CRC-bytes as well as the closing flag is appended to the last byte from the XFIFO. The last command (XRES) resets the HDLC-transmitter, aborts a HDLC-frame currently in transmission and generates an XPR-status after the command has been completed. A new frame immediately entered after the XPR-status bit was set is delayed until the abort sequence has been completed. Three state changes are indicated by the transmit FlFO-status bits. XPR indicates that the FIFO is able to load up to four new bytes to begin a message or to continue the frame. XMR indicates that the current frame has been aborted via the S/G-bit after the first FlFO-contents. The data of the frame has to be reentered. A XPR-status is generated immediately after XMR has been read to indicate that the FIFO is able to load new data. XDU indicates that the contents of the FIFO has been transmitted and no endof-frame indication was issued. The transmitted frame has been aborted by a sequence of seven `1'. XFS1 XFS0 Status State 0 0 1 1 0 1 0 1 XPR XMR XDU No status change Transmit Pool Ready Transmit Message Repeat Transmit Data Underrun Action Non or enter begin of message Enter up to four bytes Retransmit the message Frame has been aborted
Semiconductor Group
77
Operational Description
The HDLC-transmitter and the transmit buffer are controlled by two bits of the second control byte (CTRL2). HXC1 HXC0 Command 0 0 1 1 0 1 0 1 XTF State No command Transmit Transparent Frame
XTF x XME Transmit Transparent Frame and Transmit Message End XRES Transmitter Reset
3.1.4.2 HDLC-Receiver The HDLC-receive FIFO contains 2 x 4 bytes. One half of the RFIFO (top half) is connected to the receiver shift register while the second half (CPU half) is accessible from the microcontroller. Data is stored into the top half until the second half is empty. If all four bytes contain valid data or the final part of a frame is stored in the CPU half, a status bit is set. The RPF-status bit indicates that all four bytes contain valid data which do not contain the last part of a message. The RME-interrupt indicates that the final part of a message is available from the RFIFO. In this case, the value of the RBC-bits have to be evaluated to determine the number of valid bytes in the RFIFO. At the end of the RFlFO-data transfer, a RMC-command has to be issued via the CTRL2-register. This command acknowledges the previous RPF- or RME-status and empties the RFIFO so that the next part of the frame or the next frame may be transferred from the top half to the CPU half. The RMC-command may also be sent if none of the RFlFO-data has been read. The HDLC-receiver is controlled by two bits. Their combination indicates to reset the receiver, to acknowledge the RFlFO-contents, to ignore the remaining part of a frame. The later command can be used to suppress further reception of a frame after the address field has been received and it indicates a different destination. Appr. State RPF RME Receive Pool Full Action Four valid bytes are in the RFIFO. The RMC, RMD or RRES-command free's the RFIFO.
Receive Message End Up to four bytes are in the RFIFO. RBC1, 0 determine the number of valid bytes. The RMC, RMD or RREScommand free's the RFIFO.
Semiconductor Group
78
Operational Description
HRC1 HRC0 Command 0 0 0 1 RMC No command Acknowledges a previous RPF- or RME-status. The CPU RFIFO half can be used to store the next frame or the next part of a frame. The remaining part of a message is not forwarded and the receiver FIFO is cleared. The next RPF-or RME-interrupt is generated by the following HDLC-frame. HDLC-receiver is reset and the receive buffer is cleared.
1
0
RMD
1
1
RRES
3.1.4.3 Examples for the HDLC-Controller Operation Transmission of a Frame 3 Bytes and 13 Bytes A frame of three bytes may be entered during one serial access. The XTF x XME-command is set in the second control byte. The next XPR-status is generated after the closing flags has been transmitted successfully. A frame of more than 4 bytes is split into groups of four or less bytes. In case of 13 bytes, for the first and the following two blocks, the XTF-bit is set in the CTRL2-register and the XBC-value contains `11'. The XPR-status is generated if the CPU XFIFO is ready to buffer the next part of the message. The last block of a message is indicated by setting the XTF x XME-command and the generation of XPR is delayed until the closing flag has been transmitted.
Semiconductor Group
79
Operational Description
Dr
Dx
Flag Data 1 Data 2 Data 3 CRC
CRC
Flag
CS
MISO
STA1 STA 2
STA1
MOSI
CTRL1 CTRL 2 Data 1 Data 2 Data 3
CTRL1
INT CTRL1: WTC1, 2 = xx PW 5-0 = x CTRL 2: XHC1, 0 = 10 (XTF x XME) XBC 1, 0 = 10 RIE = 1 ISYNG = 0 HRC1, 0 = 00 STA 2: CI1.x = xxx XFW = 1 CI 0 = xxxx CTRL1: WTC1, 2 = xx PW5-0 = x
STA1: RPF = 0 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = xx
STA 1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx
ITD06333
Figure 46a Transmission of Frames
Semiconductor Group 80
ST1 = STA1 CLn = CTRLn Dn = Data byte n
Semiconductor Group
Flag Data 1 Data 2 Data 3 Data 4 ST1 ST 2 D1 D2 D3 D4 CL1 CL2 D5 D6 D7 D8 CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 CTRL1: WTC1, 2 = xx PW 5-0 = x STA 2: CI 1.x = xxx XFW =1 CI 0 = xxxx CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 STA 2: CI 1.x = xxx XFW =1 CI 0 = xxxx STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx
ITD06334
Dr
Figure 46b Transmission of Frames
Dx
CS
MISO
ST1
ST2
81
MOSI
CL1
CL 2
INT
CTRL1: WTC1, 2 = xx PW 5-0 = x
Operational Description
STA1: RPF = 0 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = xx
ST1 = STA1 CLn = CTRLn Dn = Data byte n
Semiconductor Group
Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 CRC CRC Flag ST1 ST 2 ST1 CL1 CL2 D 13 CL1 CTRL1: WTC1, 2 = xx PW 5-0 = x CTRL 2: XHC 1, 0 = 10 XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 00 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CTRL1: WTC1, 2 = xx PW5-0 = x STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx STA 1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx
ITD06345
Dr
Figure 46c Transmission of Frames
Dx
Data 5
Data 6
Data 7
CS
MISO
ST1 ST2
82
MOSI
CL1 CL 2 D9 D 10 D11 D12
INT
CTRL1: WTC1, 2 = xx PW 5-0 = x
CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00
Operational Description
STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx
STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx
Operational Description
Retransmission of a Frame In case the stop/go bit is evaluated for D-channel access control, the chances are that two terminals start transmitting at the same time and one has to abort its transmission and repeat the message. In this case, retransmission occurs automatically if the collision occurred within the first block of data. Otherwise, a XMR-status indicates that the message has to be retransmitted and therefore the data of the first block has to be written into the XFIFO.
Semiconductor Group
83
STn = STAn CLn = CTRLn Dn = Data byte n
Semiconductor Group
Flag Data 1 Data 2 Flag Data 1 Data 2 Data 3 ST1 ST 2 D3 D4 CL1 CL2 D 5 D6 D7 D8 CTRL1: WTC1, 2 = xx PW 5-0 = x CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx
ITD06335
Dr
Figure 47a Retransmission of a Frame
STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx
Dx
CS
MISO
ST1 ST2
84
MOSI
CL1 CL 2 D1
D2
INT
CTRL1: WTC1, 2 = xx PW 5-0 = x
CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00
Operational Description
STA1: RPF = 0 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = xx
STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx
STn = STAn CLn = CTRLn Dn = Data byte n
Semiconductor Group
Data 6 Data 7 Data 8 Data 9 Data 10 CRC CRC Flag ST1 ST2 ST1 CL1 CL 2 D9 D 10 CL1 CTRL1: WTC1, 2 = xx PW 5-0 = x CTRL 2: XHC 1, 0 = 10 XBC1, 0 = 01 RIE = 1 ISYNC = 0 HRC1, 0 = 00 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CTRL1: WTC1, 2 = xx PW5-0 = x STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx STA 1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx
ITD06346
Dr
Figure 47b Retransmission of a Frame
Dx
Data 4
Data 5
CS
MISO
85
MOSI
INT
Operational Description
Operational Description
Transmit Data Underrun In case the XFIFO becomes empty without detecting a XME-bit, the transmitter aborts the current frame by an abort sequence and the XDU-status is indicated.
STn = STAn CLn = CTRLn Dn = Data byte n Dr
Dx
Flag
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 7x1
CS
MISO ST1 ST2
ST1 ST2
ST1
ST1
MOSI CL1 CL2 D1 D2 D3 D4
CL1 CL2 D5 D6 D7 D8
INT CTRL2: CTRL1: WTC1, 2 = xx RIE = 1 ISYNC = 0 PW5 - 0 = x HRC1, 0 = 00 XHC1, 0 = 01 XBC1, 0 = 11 STA1: RPF = 0 RME = 0 XFS1, 0 = 00 CIC = x RBC1, 0 = xx STA2: CI1.x = xxx XFW = 1 CI0 = xxxx CTRL1: CTRL2: WTC1, 2 = xx RIE = 1 PW5 - 0 = x ISYNC = 0 HRC1, 0 = 00 XHC1, 0 = 01 XBC1,, 0 = 11 STA1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx STA2: CI1.x = xxx XFW = 1 CI0 = xxxx CTRL1: WTC1, 2 = xx PW5 - 0 = x CTRL1: WTC1, 2 = xx PW5 - 0 = x
STA1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx
STA1: RPF = 0 RME = 0 XFS1, 0 = 11 CIC = x RBC1, 0 = xx
ITD06336
Figure 48 Transmit Data Underrun
Semiconductor Group 86
Operational Description
Reception of a Frame with 3 Bytes and with 13 Bytes The RPF- or RME-bit indicate that valid data is in the RFIFO. Both RPF- and RME-status have to be served within 2 ms to prevent an underrun condition indicated by the RDO-bit in the RSTA-value.
Dr Dx
Flag Data 1 Data 2 Data 3 CRC
CRC
Flag
CS
MISO
STA1 STA2 Data 1 Data 2 Data 3 RSTA
MOSI
CTRL1 CTRL2
INT CTRL2: CTRL1: WTC1, 2 = xx XHC1, 0 = 00 XBC1, 0 = 00 PW5 - 0 = x RIE = 1 ISYNG = 0 HRC1, 0 = 01 (RMC) STA1: RPF = 0 RME = 1 XFS1, 0 = 00 CIC = x RBC1, 0 = 00 STA2: CI1.x = xxx XFW = 1 CI0 = xxxx
ITD06337
Figure 49a Reception of Frames
Semiconductor Group 87
Dr
Flag
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data 10
Semiconductor Group
ST1 ST2 D1 D2 D3 D4 CL1 CL2 CTRL 2: CTRL1: WTC1, 2 = xx XHC 1, 0 = 00 PW 5-0 = x XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 01 (RMC) STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx STA1: RPF = 1 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = 00
ITD06338
Figure 49b Reception of Frames
Dx
CS
MISO
88
MOSI
INT
Operational Description
Dr
Data 11
Data 12
Data 13
CRC
CRC
Flag
Semiconductor Group
D6 ST1 ST2 D7 D8 D9 D10 D11 D12 ST1 ST2 D13 RST CL1 CL2 CL1 CL2 CTRL 2: CTRL1: WTC1, 2 = xx XHC1, 0 = 00 PW5-0 = x XBC 1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 01 (RMC) STA 2: CI1.x = xxx XFW = 1 CI 0 = xxxx STA 1: RPF = 1 RME = 0 XFS1, 0 = 00 CIC = x RBC1, 0 = 00 CTRL 2: CTRL1: WTC1, 2 = xx XHC 1, 0 = 00 PW 5-0 = x XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 01 (RMC) STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx STA1: RPF = 0 RME = 1 XFS 1, 0 = 00 CIC = x RBC1, 0 = 10
ITD06347
Figure 49c Reception of Frames
Dx
CS
MISO
ST1 ST2
D5
MOSI
CL1
CL2
89
INT
CTRL 2: CTRL1: WTC1, 2 = xx XHC 1, 0 = 00 PW 5-0 = x XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 01 (RMC)
Operational Description
STA1: RPF = 1 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = 00
STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx
Operational Description
Full Duplex Operation In case of a full duplex operation where a frame is received at the same time one is transmitted, an optimization of the serial interface service is possible. The ISYNC-bit in the CTRL2-value selects whether receive and transmit interrupts occur at any time or if the interrupt is generated only if both status bits are active. To use the synchronization it is necessary that the third XPR-status has been indicated since this guarantees that the transmission of the frame has not been stopped within the first bytes. After the third XPR-status is detected, the ISYNC-bit may be set and the following interrupts are delayed until both a receive and transmit status is set. After the XTF x XME-command is set or a XMR-status has been indicated it is recommended to disable the synchronous interrupt generation again.
Semiconductor Group
90
STn = STAn CLn = CTRLn Dn = Data byte n Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10
Semiconductor Group
Flag Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 ST1 ST 2 ST1 ST2 D 1 D2 D3 D4 D2 D3 D4 CL1 CL2 D5 D6 D7 D8 CL1 CL 2 CTRL 2: CTRL1: WTC1, 2 = xx XHC 1, 0 = 01 PW 5-0 = x XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CTRL 2: CTRL1: WTC1, 2 = xx XHC1, 0 = 00 PW5-0 = x XBC 1, 0 = 00 RIE= 1 ISYNC = 0 HRC1, 0 = 01 STA 2: CI1.x = xxx XFW = 1 CI 0 = xxxx STA 1: RPF = 1 RME = 0 XFS1, 0 = 00 CIC = x RBC1, 0 = 00 STA1: RPF = 0 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = xx
ITD06339
Dr
Flag
Data 1
Figure 50a Full Duplex Operation
Dx
CS
MISO
ST1 ST2
91
MOSI
CL1 CL 2
D1
INT
CTRL 2: CTRL1: WTC1, 2 = xx XHC 1, 0 = 01 PW 5-0 = x XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00
Operational Description
STA1: RPF = 0 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = xx
STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx
STn = STAn CLn = CTRLn Dn = Data byte n Flag
Semiconductor Group
Data 9 Data 10 Data 11 Data 12 Data 13 CRC CRC Flag ST1 ST2 D5 D6 D7 D8 ST1 ST 2 D 9 D10 RST ST1 CL1 CL 2 D13 CL1 CL2 CL1 CTRL1: WTC1, 2 = xx PW 5-0 = x CTRL 2: XHC 1, 0 = 10 XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 01 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CTRL1: WTC1, 2 = xx PW5-0 = x CTRL 2: XHC1, 0 = 00 XBC 1, 0 = 00 RIE = 1 ISYNC= 0 HRC1, 0 = 01 STA 1: RPF = 0 RME = 0 XFS1, 0 = 00 CIC = x RBC1, 0 = 11 STA 2: CI1.x = xxx XFW = 1 CI 0 = xxxx CTRL1: WTC1, 2 = xx PW5-0 = x STA1: RPF = 1 RME = 1 XFS 1, 0 = 01 CIC = x RBC1, 0 = 00 STA 1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx
ITD06348
Dr
Data 10
CRC
CRC
Figure 50b Full Duplex Operation
Dx
Data 7
Data 8
CS
MISO
ST1 ST 2
92
MOSI
CL1 CL2 D 9 D10 D11 D12
INT
CTRL1: WTC1, 2 = xx PW 5-0 = x
CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 1 HRC1, 0 = 00
Operational Description
STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx
STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx
Operational Description
Ignoring the Rest of a Message The reception of a frame may be ignored after the first bytes have been read until the frame is completed. This feature is provided instead of an address recognition feature. In this case, a RPF-interrupt indicates the first block of data and the corresponding FlFO-data is read. At the event of the next RPF-interrupt, the RMD-bit may be set in the CTRL2-value to set the corresponding command. Afterward, the next RPF- or RME-status is generated for the next frame.
Semiconductor Group
93
Dr
Flag
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 CRC
CRC
Flag
Semiconductor Group
ST1 ST2 D1 D2 D3 D4 ST1 ST2 CL1 CL2 CL1 CL2 CTRL 2: CTRL1: CTRL1: WTC1, 2 = xx XHC 1, 0 = 00 WTC1, 2 = xx PW 5-0 = x XBC1, 0 = 00 PW 5-0 = x RIE = 1 ISYNC = 0 HRC1, 0 = 01 (RMC) STA1: RPF = 1 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = 00 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx STA1: RPF = 1 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = 00 CTRL 2: XHC 1, 0 = 00 XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 10 (RMC) STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx
ITD06340
Dx
Figure 51 Ignoring the Rest of a Message
CS
MISO
MOSI
94
INT
Operational Description
Operational Description
3.1.5
Reset
Reset Logic While the power-on reset pulse is generated or an external reset is applied, pins which operate as l/O-pins are configured as inputs. The Upn-awake detector becomes active after reset. IOM-clocks signals are active in TE-mode. BCL, SDS remain `0' because of the CTRL4-reset value. PWO/Ring/Mode is `0' because of the CTRL1- and CTRL3-reset values. The registers of the SmartLink-P are reset to the default values. Table 3 Reset State of the SmartLink-P Registers Register STA1 STA2 CTRL1 CTRL2 CTRL3 Value after Reset 00H 00H 00H 00H 00H Meaning No C/I-change, no status change, no data in RFIFO. C/I is `1111'. MCLK = 3.84 MHz, Watchdog disabled, PW = `000000'. No HDLC-controller operation, no XFIFO-data. Permanent D-channel access, permanent access to C/I-channel 0 and D-channel. T-channel mapped on S/G, PW-output operates as LCD-contrast, TlC-bus access during D-channel transmission only, TAD = `000'. Normal operation of DU-line, Serial Strobe = `000' (OFF), Cl0 = `0000'.
CTRL4
00H
When using the undervoltage detection for reset generation, a short internal reset is generated which resets the internal functions and starts the 56 ms counter. The lOM-clocks will be stopped after the Upn-transceiver enters its deactivated state. As a result, external transceiver devices (SBCX, PSB 21810 or SmartLink in TR-mode) can not leave their reset state and they can not start activation of the IOM-2 interface. The terminal software has to enable the IOM-clocks by the SPU-bit and output the C/I-command `RES' to guarantee a correct reset of all other transceiver devices.
Semiconductor Group
95
Operational Description
3.1.6
Initialization
During initialization the control registers have to be setup. The necessary setup is listed in table 4. Table 4 Initialization of the SmartLink-P Registers Register Bit CTRL1 PRE WTC PW XRES RRES SGE, TBU SGM, BAC, TAD LCRI SPU CI0 Effect MCLK-clock rate Watchdog enable if required LCD-contrast value/Ringing frequency Reset the HDLC-receiver and transmitter Select TlC-bus, S/G-operation,T-channel mapping, TlC-bus address. LCD-contrast or ringer operation of PWM Awake the lOM-interface until the received C/l-code indicates PU. Afterwards reset SPU to `0' and enter TIM or ARx in the CI0 bits. Program strobe signal Application Restricted to
CTRL2 CTRL3
CTRL4
SDS
3.2 3.2.1
TR-Mode Control of the Upn-Transceiver
3.2.1.1 Activation/Deactivation of the IOM(R)-2 Interface The Upn-transceiver functions are controlled by commands issued by the SmartLink-P depending on the current state. In downstream direction, only the commands `DR', `AR' and `DI' trigger the state machine. In upstream direction, the four indications `TIM', `AR', `AI' or `DC' are generated. If the IOM-2 interface is turned off, an asynchronous awake procedure is initiated if the SmartLink-P in TR-mode request an activation procedure.
Semiconductor Group
96
Operational Description
In TR-mode, the length of the FSC-signal is monitored to avoid misalignment of internal buffers in case incorrect pulses on FSC have been detected. The state-machine of the Upn-transceiver is reset every time, a FSC-period of less than 96 bits is detected. The SmartLink generates a reset signal for the state machine which is active for 6 lOM-frames. As a result, 4 or 5 info 0 frame will be transmitted on Upn to force the TE-device in the level detect (Resynchronization) state. This number of info 0 frames is still less than is required to detect info 0 by the TE-device (2 ms, 8 info 0 frames). 3.2.1.2 Layer-1 Command/Indication Codes in TR-Mode Command (downstream) Abbr. Deactivate request Activate request DR AR, AI, ARL2, AIL2 DC Code 0000 1xx0 Transmission of info 2 and info 4 according to the Upn-procedure Info 0 or Dl received after deactivation request or no TlC-bus request Remarks
Deactivation confirmation
1111
Indication (upstream) Timing Activate request Activate indication Deactivation indication
Abbr. TIM AR AI DI
Code 0000 1000 1100 1111
Remarks Deactivation state, activation from the line not possible Info 1 received
Deactivation acknowledgment, quiescent state
In TR-mode, the Upn-interface is activated if the C/l-code Activate Request (AR, ARL2) or Activate Indication (Al, AIL2) has been detected in downstream direction. It stays activated until the C/l-code Deactivate Indication (Dl) is received in downstream direction.
Semiconductor Group
97
Operational Description
3.2.1.3 State Diagrams In TR-mode the layer-1 (Upn) part of the PSB 2197 SmartLink-P is a IOM-2 interface slave in any aspect. Therefore it is also able to activate the IOM-2 interface by pulling the data upstream line to zero asynchronously. Since the PSB 2197 SmartLink-P in TR-mode is a stand alone function without microprocessor aid, the PSB 2197 SmartLink-P in TR-mode will indicate the activated state of the slave Upn-interface by pulling bit 6 of the C/I-channel 1 on the data upstream line to `0'. The presence of a SmartLink-P in TR-mode is indicated by pulling bit 5 of the C/I-channel 1 on the data upstream line to `0'. 7 CI1 1/0 0 (activated) MR 0 MX
Semiconductor Group
98
Operational Description
3.2.1.4 TR-Mode State Description Pending Deactivation State after reset or deactivation from the IOM-2 interface by command `Dl'. Note that no activation from the network side is possible starting from this state. Wait for DR This state is entered from the pending deactivation state once info 0 has been identified or after the command `Dl'. Deactivated The Upn-interface is deactivated and the IOM-2 interface is or will be deactivated. Activation is possible from the Upn-interface and from the IOM-2 interface. If activation is initiated by the terminal side it first leads to the activation of the IOM-2 interface by the indication `TIM' (Awake: DU pulled to VSS asynchronously, later on synchronously). Pending Activation 1 After activation from the line has been started the indication Activation Request (AR) is issued to get synchronization from the upstream network side. Pending Activation 2 Upon the command Activation Request (AR) the PSB 2197 SmartLink-P transmits the 4-kHz info 2 towards the network, waiting for info 1. Synchronized The Upn-receiver is synchronized and detects info 1. It continues the activation procedure by transmission of info 4. Activated The (Upn)-receiver is synchronized and detects info 3. The activation procedure is now completed and B1-, B2-, and downstream D-channels are conveyed transparently. For transmission of the upstream D-channel the TlC-bus function applies. Resynchronization Under severe disturbances on the line the Upn-receiver still recognizes the receipt of a signal but is no more synchronized.
Semiconductor Group
99
Operational Description
RES AR, ARL 2 AI, AIL 2 TIM 2) X
Pend. Deactivation i0 i0 i0 + DC DI X
AR, ARL 2 AI, AIL 2
Wait for DR i0 i0 DC DI Awake DC DR i0 i0 AR 2) AR, ARL 2 AI, AIL 2 DI DR DR DR DR Pend. Activation 1 i0 i1w AR, ARL 2 AI, AIL 2 i1w
Deactivated
Pend. Activation 2 i2 i1 DI i1 DI DR i1 x i3 DR i3 AI 1) i3 DR DR U pn IOM
R
i1
DR DR
Synchronized i4 i1
Resynchronization i2 i1
OUT
IN
Ind.
Cmd.
Activated i4 i3
State ix ir
1) : Transmitted after TIC bus access only if upstream T-channel is '1' otherwise DI is transmitted 2) : Transmitted after TIC bus access otherwise DI is transmitted R Awake : DU- line pulled to VSS for T4 if i1w is detected and IOM is deactivated
ITD05372
Figure 52 State Diagram TR-Mode
Semiconductor Group 100
Operational Description
3.2.1.5 Example of the Activation/Deactivation Figure 53 shows the activation/deactivation procedure between the SmartLink-P operating in TR-mode and a SmartLink-P on the slave terminal.
TE2 DC DI INFO 0
TR DC DI
TE 1 INFO 0
LC DC Deactivated DI State
~ ~
SPU = 1 PU AR, SPU = 0
~ ~
INFO 1w
~ ~
~ ~
Awake T4 AR PU
~ ~
~ ~
~ ~
~ ~
INFO 1w INFO 2 T1 T1 AR T2 RDS T3 AI Activated State INFO 0 INFO 1 INFO 4 INFO 3
INFO 2 T1 RSY AR T3 AI T2 INFO 0 INFO 1 INFO 4 INFO 3 T3 T2
RSY AR
T2 T3
AI
~ ~
T4 DR DC DI
~ ~
INFO 0 INFO 0
~ ~
~ ~
DR TIM T4 DC PU
~ ~
T4
~ ~
INFO 0 INFO 0
~ ~
~ ~
DR T4
INFO 0 DI
INFO 0
DC Deactivated DI State
IOM -2
R
U pn Interface
IOM -2
R
U pn Interface
IOM -2
ITD05373
R
Figure 53 Activation/Deactivation (TR, TE)
Semiconductor Group 101
Operational Description
3.2.2
D-Channel Access Procedure
The TR-mode uses the TlC-bus access procedure to access the upstream D-channel if requested by the terminal connected to the Upn-interface. TCM (T-Channel Mode) selects the control of the downstream T-channel source. If TCM is `0', the downstream T-channel transmits the inverse value of the received stop/go bit. This is the regular operation for terminal repeater applications. If TCM is `1', the downstream T-channel is controlled by the received CI0-indication. If CI0 is different from `AI' (`1100'), the T-channel is set to `0'. While C/l indicates `AI', the T-channel is set to permanent `1'. Double last look is active so that the CI0-lndications must be received twice before the T-channel changes. This mode is necessary to operate together with the IEC-Q since the IEC-Q doesn't generate a stop/go bit so it remains `1' which would indicate stop. The terminal repeater enables the T-channel after activation is completed as long as the primary link (2B1Q) is in the activated state. TCM = `1' also disables the TIC-bus access and the output of CI1 bits. The SmartLink outputs the CI0-bits and the D-bits on the DU-line permanently. If TCM changes from `0' to `1' during operation, the change becomes effective immediately and a TIC-bus access is aborted. From that moment on, no further TIC-bus accesses are performed. TlC-Bus Access (TCM = `0' only) Idle The idle state is specified by the TlC-bus address as `111' and the BAC-bit set to `1'. During this state, the upstream D-channel is transparent and the downstream T-bit transmits the inverse of the stop/go bit. TlC-Bus Access by other D-Channel Sources If the TlC-bus is occupied by another source which is indicated by the TlC-bus address different from `111' or the BAC-bit set to `0', the downstream T-bit changes to the block value (T = `0'). TlC-Bus Request by Upn-Receiver Upon a T = `1' bit received from the slave terminal which is interpreted as a D-channel access request the PSB 2197 SmartLink-P tries to access the TlC-bus according to the specified procedure using TlC-bus address `011'. After the TlC-bus has been occupied the inverse of the S/G-bit position is transmitted via the Upn T-bit.
Semiconductor Group
102
Operational Description
If the T-channel becomes `0' again, the TlC-bus is released after a delay of two IOM-2 frames. The SmartLink in TE-mode guarantees that at least one T-bit set to `0' is transferred between two HDLC-frames, thus a HDLC-frame of the master can be inserted. Blocked Condition during a Frame Transmission If a blocked condition occurs during the transmission of a frame, the S/G-bit changes to stop and no further D-bits are output to the IOM-2 interface. The stop condition changes the downstream T-bit to a blocked state and the HDLC-transmitter in the slave terminal aborts the frame. If the upstream T-bit remains `0' (BAC-bit of the terminal), the TR SmartLink-P retains its TlC-bus access to make sure that the slave terminal can transmit a frame if the stop/go bit becomes `Go' again. 3.2.3 Reset State
The reset state is entered after applying an active signal to the reset input. In reset state, the transceiver state machine is reset and info 0 is output on the Upn-interface. The TlC-bus access state machine is also reset so that the TlC-bus becomes idle.
Semiconductor Group
103
Operational Description
3.3 3.3.1
HDLC-Controller Mode Interrupt Structure and Logic
The interrupt structure in HDLC-controller mode is identical to the TE-mode. 3.3.2 Control of the Serial Control Interface
The control of the serial control interface is identical to the TE-mode. 3.3.3 Control of the HDLC-Data Transfer
The control of the HDLC-data transfer is identical to the TE-mode. 3.3.4 Control of Terminal Specific Functions
Control of Upstream C/l 7 to 5 In HDLC-controller mode the control of Cl1 bit 7 to 5 in upstream direction (DU) is done by the least significant three bits of CTRL1. Generation of Bit Clock and Strobe Signals The SDS-bits in CTRL4 control the generation of BCL-clocks and the output of the SDS-pin. 3.3.5 Reset
The reset state is identical to the TE-mode.
Semiconductor Group
104
Register Description
4
Register Description
The parameterization of the SmartLink-P and the transfer of data and control information between the microprocessor and the SmartLink-P is performed through a set of registers. Table 5 SmartLink-P Register Map (TE) Bit 7 PRE1/ WTC1 HXC1 SGE SPU PRE0/ WTC2 HXC0 TBU SDS2 PW5 XBC1 TCM SDS1 PW4 XBC0 LCRI SDS0 PW3 RIE BAC CI0 PW2 ISYNC TAD2 CI0 PW1 HRC1 TAD1 CI0 Bit 0 PW0 Reg. R/W
CTRL1 W
HRC0 CTRL2 W TAD0 CI0 CTRL3 W CTRL4 W XFIFO W
RPF
RME
XFS1
XFS0 XFW
RFO CI0
CIC CI0
RBC1 CI0
RBC0 STA1 CI0 STA2
R R
CI1Bit7 CI1Bit6 CI1Bit5
RFIFO R VFR RDO CRC RAB 0 0 0 0 RSTA R
SmartLink-P Register Map (HDLC-Controller Mode) Bit 7 0 HXC1 SGE SPU 0 HXC0 TBU SDS2 0 XBC1 TCM SDS1 0 XBC0 0 SDS0 0 RIE BAC CI0 Bit 0 Reg. R/W
CI1Bit7 CI1Bit6 CI1Bit5 CTRL1 W ISYNC TAD2 CI0 HRC1 TAD1 CI0 HRC0 CTRL2 W TAD0 CI0 CTRL3 W CTRL4 W XFIFO W
RPF
RME
XFS1
XFS0 XFW
RFO CI0
CIC CI0
RBC1 CI0
RBC0 STA1 CI0 STA2 RFIFO
R R R R
CI1Bit7 CI1Bit6 CI1Bit5
VFR
RDO
CRC
RAB
0
105
0
0
0
RSTA
Semiconductor Group
Register Description
4.1 CTRL1
SmartLink-P Register Summary Control Byte 1 (TE-Mode)
Value after reset: 00H Bit 7 0H PRE1/ PRE0/ WTC1 WTC2 PW5 PW4 PW3 PW2 PW1 Bit 0 PW0 Reg. R/W
CTRL1 W
PRE1, 0
Prescaler Value The PRE1, 0 bits control the microcontroller clock output. If both bits are `11', the contents of PW1 and PW0 is latched and specifies the frequency. PRE1 1 1 1 1 PRE0 1 1 1 1 PW1 PW0 MCLK-clock frequency 0 0 1 1 0 1 0 1 3.84 MHz 7.68 MHz 1.92 MHz 0.96 MHz
WTC1, WTC2
Watchdog Timer Control During every time period of 56 ms the processor has to program the WTC1- and WTC2 bit in the following sequence to reset and restart the watchdog timer: WTC1 WTC2 1 0 0 1
The watchdog timer is enabled by the first `10' sequence. As long as both bits are `00', the watchdog is not active. `11' has no impact on the watchdog but controls the microcontroller clock output frequency.
Semiconductor Group
106
Register Description
PW5-0
Pulse Width 5-0 Specifies the output of the pulse width generator dependend on the setting of LCRI-control bit (CTRL3). CTRL3: LCRI = 0 (LCD-contrast output) PW5-4 00 00 ... 00 00 1110 1111 On period: 14/15 On (high) PW3-0 PW output 0000 0001 Off (low) On period: 1/15
PW5-4 have to be `00'. CTRL3: LCRI = 1 (Ringing output) PW5-0 Frequency 000000 PWO/Ring output is tristate 000001 8000 Hz 000010 5333 Hz 000011 4000 Hz 111110 253.96 Hz 111111 250 Hz The value n (PW5-0) specifies a divider. The output frequency is calculated based on the following formula:
f = 16 kHz / (n + 1)
Semiconductor Group
107
Register Description
CTRL1
Control Byte 1 (HDLC-Controller Mode)
Value after reset: 00H Bit 7 0H 0 0 0 0 0 Bit 0 Reg. R/W
CI1Bit7 CI1Bit6 CI1Bit5 CTRL1 W
Controls the bit 7 to 5 of the command/indicate channel 1 on data upstream. Cl1Bit7 0: 1: Cl1Bit6 0: 1: Cl1Bit5 0: 1: Cl1Bit5 = 1 Cl1Bit5 = 0 Cl1Bit6 = 1 Cl1Bit6 = 0 Cl1Bit7 = 1 Cl1Bit7 = 0
Semiconductor Group
108
Register Description
CTRL2
Control Byte 2
Value after reset: 00H Bit 7 1H HXC1 HXC0 XBC1 XBC0 RIE ISYNC HRC1 Bit 0 Reg. R/W
HRC0 CTRL2 W
Note: The HDLC-controller operates on DCL/2 clock rate. lt requires 4 clock cycles to execute a command entered in the CTRL2-register. After a FlFO-part has been transferred, the corresponding interrupt is generated immediately. HXC1, 0 HDLC-Transmitter Control 1, 0 HXC provides the commands for the HDLC-transmitter: HXC1 0 0 1 HXC0 0 1 0 Command No command, XBC selects whether CTRL3 and 4 is transmitted XTF, Transmit Transparent Frame. XBC determines the number of valid, XFlFO-bytes to follow. XTF x XME, Transmit Transparent Frame and Transmit Message End. XBC determines the number of valid XFlFO-bytes to follow. XRES, Transmitter Reset
1 XBC1, 0
1
Transmit Byte Count 1, 0 Indicates the number of valid bytes for the XFIFO which follow after the control bytes if HXC1, 0 is not `00'. XBC1 0 0 1 1 XBC0 0 1 0 1 Transmit Byte Count 1 Byte 2 Bytes 3 Bytes 4 Bytes
If HXC1, 0 = `00', XBC1, 0 selects whether CTRL3 and CTRL4 are transmitted after CTRL2. XBC1 0 0 XBC0 0 1 No valid data follows after CTRL2. CTRL3 and CTRL4 follow after CTRL2.
Semiconductor Group
109
Register Description
RIE
Receiver Interrupt Enable RIE controls the generation of receive interrupts. 0: 1: Receiver interrupts are masked. Receiver interrupts are enabled. An interrupt is generated if four bytes are valid in the RFIFO (RPF) or if the RME-bit is set.
ISYNC
Interrupt Synchronization Used to synchronize transmit and receive interrupts to allow simultaneous access to the XFIFO and RFIFO. 0: 1: RPF-, RMEsynchronized. and XFS-interrupt generation is not
An interrupt is generated only if both a receive interrupt (RPF, RME) and a transmit interrupt (XFS1, XFS0) is active.
HRC1, 0
HDLC Receiver Control 1, 0 HRC provides the commands for the HDLC-receiver: HRC1 0 0 1 1 HRC0 0 1 0 1 Command No command RMC, Receive Message Complete RMD, Receive Message Delete RRES, Receiver Reset
Semiconductor Group
110
Register Description
CTRL3
Control Byte 3
Value after reset: 00H Bit 7 2H SGE SGE TBU TCM LCRI BAC TAD2 TAD1 Bit 0 Reg. R/W
TAD0 CTRL3 W
Stop/Go Bit Evaluation Specifies whether the S/G-bit is evaluated for D-channel transmission. 0: 1: Permanent D-channel transmission. D-channel transmission only during S/G = `go'.
TBU
TIC-Bus Used Specifies whether the TlC-bus procedure is used to gain access to the C/l-channel 0 and D-channel. 0: 1: Permanent access to the C/l-channel 0 and D-channel. TlC-bus procedure is used to access the upstream C/I-channel 0 and D-channel. The TIC-bus address is specified in bit 0 to 2.
TCM
T-Channel Mapping 0: 1: T-channel data is mapped onto the S/G-bit (S/G = inverse T-channel). T-channel data is mapped onto the AB-bit (AB = T-channel).
LCRI
LCD-Contrast/Ringing Output (used in TE-Mode only) 0: Pulse width output operates as LCD-contrast output. PW-0 specifies the on-to-off ratio of a fixed frequency signal. PW5-4 have to be `00'. Pulse width output operates as ringing output. PW5-0 specifies the ringing frequency.
1:
BAC
TIC-Bus Access Forces the SmartLink-P to occupy the TIC-bus without transmission of D-channel data. Valid only if TBU is `1'. 0: 1: TIC-bus used for D-channel data transmission only. TIC-bus accessed permanently.
Semiconductor Group
111
Register Description
TAD2-0
TIC-Bus Address Specifies the TIC-bus address used by the SmartLink-P. TAD2 0 0 0 ... 1 1 1 1 0 1 6 7 (lowest priority) TAD1 0 0 1 TAD0 TIC-bus address 0 1 0 0 (highest priority) 1 2
Semiconductor Group
112
Register Description
CTRL4
Control Byte 4
Value after reset: 0FH Bit 7 3H SPU SPU SDS2 SDS1 SDS0 Software Power-Up 0: 1: Normal operation of DU. DU is pulled low while SPU = `1'. Used to awake the IOM-interface. CI0 CI0 CI0 Bit 0 CI0 Reg. R/W
CTRL4 W
SDS2-0
Serial Data Strobe Controls the generation of the serial data strobe signal and the BCL-signal. SDS2-0 also specify whether B-channel information is looped or the upstream B-channel information is muted.
SDS2 0 0 SDS1 0 0 SDS0 0 1 Function of SDS SDS low, BCL low SDS high during IC1, BCL active Upstream Time-Slot Data Transparent Transparent
0
1
0
SDS high during B1, Transparent BCL active SDS high during B2, Transparent BCL active SDS low, BCL low Downstream B1 looped to upstream B1 Downstream B2 looped to upstream B2
0
1
1
1
0
0
1
0
1
SDS low, BCL low
1
1
0
SDS high during B1, Upstream B1 muted BCL active SDS high during B2, Upstream B2 muted BCL active
1
1
1
Semiconductor Group
113
Register Description
B-Channel Looping During the B-channel loop selected by the SDS-bits, the received B-channel data from the Upn-interface is output on the DD-line and looped back to the DU-line. The DU-line is not disconnected which means that the external components on the DU-line must output `FF' during the B-channel time-slot which is looped back. Otherwise the information is `ored' in terms of a `0' bit overwriting a `1' bit. The advantage of this method is that monitoring is possible on the lOM-interface pins. B-Channel MUTE While the B-channel MUTE function is active, the connection between the external DU-line and the internal B-channel input line is disconnected and the B-channel input sees only `1's. The DU-line will still show the output of the codec but the Upn-B-channel information is `FF'. This implementation provides no easy method to check the MUTE function since the B-channel information is scrambled before it is transmitted on the Upn-interface. CI0 Command/Indicate Channel 0 Value which is transmitted on the upstream C/l-channel 0 depending on the BAC and TBU bit.
Semiconductor Group
114
Register Description
STA1
Status Byte 1
Value after reset: 00H Bit 7 0H RPF RPF RME XFS1 XFS0 RFO CIC Bit 0 Reg. R/W R
RBC1 RBC0 STA1
Receive Pool Full Indicates that a part of a message is stored in the RFIFO. All four bytes contain valid data.
RME
Receive Message End Indicates that the last part of a message is stored in the RFIFO. The RBC1, 0-value indicates the number of valid bytes in the RFIFO. This number includes the RSTA-value.
XFS1, XFS0
Transmit FIFO-Status Indicates the status of the transmit FIFO. XFS1 0 0 1 XFS0 0 1 0 XPR Appr. Transmit FlFO-Status No change in the transmit FlFO-status. Transmit Pool ready. Up to four bytes may be entered.
XMR Transmit message repeat. The S/G-bit became stop and the frame has to be reentered. Up to four bytes may be entered. XDU Transmit Data Underrun. The transmitter became empty without XME-marking. The frame is aborted (7 `1'). The XFIFO is cleared and new data may be entered.
1
1
The generation of the XPR-status is delayed until the closing flag has been transmitted completely if the previous transmitter command was XME. RFO Receive Frame Overflow The begin of an HDLC-frame (1st byte) could not be stored since the RFIFO is full.
Semiconductor Group
115
Register Description
CIC
C/I-Code Change Indicates that a new C/l-code is available in STA2. 0: 1: No C/l-code change C/l-code change occurred. The new value is stored in the STA2-register.
RBC1, 0
Receive Byte Count Indicates the number of valid bytes in the RFIFO if a RME-status bit is set to `1'. This value is repeated while STA1 is read until the RMC, RMD or RRES is issued. It is not changed by reading the RFIFO. RBC1 0 1 1 0 RBC0 1 0 1 0 Number of valid bytes in the RFIFO 1 Byte 2 Byte 3 Byte 4 Byte
If RME or RPF is `0', the RBC1, 0-values may have any value and should be ignored by the software.
Semiconductor Group
116
Register Description
STA2
Status Byte 2
Value after reset: 0FH Bit 7 1H CI1Bit7 CI1Bit6 CI1Bit5 XFW C/I-Channel 1 Bit 7 Indicates the state of bit 7 on the upstream C/I-channel 1. This bit is reserved to indicate the presence of a SmartLink-S in LT-S mode. 0: 1: CI1Bit6 C/I-channel 1 bit 7 is `0' (SmartLink-S present) C/I-channel 1 bit 7 is `1' (SmartLink-S not present) CI0 CI0 CI0 Bit 0 CI0 Reg. STA2 R/W R
CI1Bit7
C/I-Channel 1 Bit 6 Indicates the state of bit 6 on the upstream C/l-channel 1 to indicate the active state of the slave Upn-interface. 0: 1: C/I-channel 1 bit 6 is `0' (Slave Upn activated) C/I-channel 1 bit 6 is `1' (Slave Upn not activated)
CI1Bit5
C/I-Channel 1 Bit 5 Indicates the state of bit 5 on the upstream C/l-channel 1 to detect the presence of the slave Upn-interface. 0: 1: C/I-channel 1 bit 5 is `0' (TR SmartLink-P present) C/I-channel 1 bit 5 is `1' (TR SmartLink-P not present)
XFW
Transmit FIFO Write Enable Indicates that the XFIFO is able to receive new data. XFW is a static indication. It changes its state after a transmit command has been executed internally or if the XFIFO becomes empty. 0: 1: XFIFO is not empty XFIFO is empty. The next part of the frame or a new frame may be entered.
The generation of the XFW-status bit is delayed until the closing flag has been transmitted completely if the previous transmitter command was XME. CI0 C/I-Code 0 Indicates the received (downstream) C/I-code of channel 0.
Semiconductor Group 117
Register Description
RSTA Bit 7 VFR VFR
Receiver Status Byte Bit 0 RDO CRC RAB 0 0 0 0 Reg. R/W
Valid Frame Indicates that the frame consists of multiples of 8 bits and the minimum number of bytes between two flags was 3.
RDO
Receive Data Overflow Indicates that the RFIFO was not serviced in time and that at least one byte of the message could not be stored. 0: 1: No data lost At least one byte lost
CRC
CRC-Check Correct Indicates whether a CRC-check was okay or not. 0: 1: CRC error CRC okay
RAB
Receiver Abort Indicates that the frame was not closed by a flag but by an abort sequence (7 `1'). 0: 1: Frame closed with flag Frame closed with abort sequence
Semiconductor Group
118
Electrical Characteristics
5
Electrical Characteristics
Absolute Maximum Ratings Parameter Voltage on any pin with respect to ground Ambient temperature under bias Storage temperature Symbol Limit Values - 0.4 to VDD + 0.4 0 to 70 - 65 to 125 Unit V C C
VS TA Tstg
DC-Characteristics TA = 0 to 70 C; VDD = 5 V 5 %, VSS = 0 V
Parameter Symbol min. L-input voltage Limit Values typ. max. 0.8 V All pins except Lla, Llb All pins except Lla, Llb Unit Test Condition Remarks
VIL
- 0.4
H-input voltage
VIH
2.0
VDD + 0.4 V
L-output voltage VOL L-output voltage 1 VOL1 H-output voltage
0.45 0.45
V V
IOL = 2 mA IOL = 7 mA
(DD, DU only)
All pins except Lla, Llb All pins except Lla, Llb, MISO MISO
VOH VOH1 VOH
2.4
VDD - 0.5 VDD - 0.5
V V
IOH = - 400 A IOH = - 100 A IOH = - 1 mA
H-output voltage
V
Semiconductor Group
119
Electrical Characteristics
DC-Characteristics (cont'd) TA = 0 to 70 C; VDD = 5 V 5 %, VSS = 0 V
Parameter Symbol min. Power supply current TE-mode operating Limit Values typ. max. 10 15 mA DCL = 1.536 MHz Unit Test Condition Remarks
ICC
VDD = 5 V inputs at VSS/VDD, no output loads except Lla, Llb; Lla, Llb load 15 mA VDD = 5 V
inputs at VSS/VDD, no output loads.
TE-mode ICC deactivated, IOMclocks stopped
9
mA
DCL = 0 MHz
TR-mode operating
ICC
8.5
mA
DCL = 1.536 MHz
VDD = 5 V
inputs at VSS/VDD, no output loads except Lla, Llb; Lla, Llb load 15 mA
TR-mode deactivated, IOM stopped
ICC
7.5
mA
DCL = 0 MHz
VDD = 5 V
inputs at VSS/VDD, no output loads.
HDLC controller mode
ICC
4.5
mA
DCL = 1.536 MHz
VDD = 5 V
inputs at VSS/VDD, no output loads.
Input leakage current Output leakage current Transmitter output impedance Receiver input impedance
ILI ILO
10
10 10
A A
0 V < VIN < VDD 0 V VOUT VDD
All pins except Lla, Llb
30
IOUT = 20 mA VDD = 5 V
transmitter inactive
Lla, Llb
10
k
Lla, Llb
Semiconductor Group
120
Electrical Characteristics
DC-Characteristics (cont'd) TA = 0 to 70 C; VDD = 5 V 5 %, VSS = 0 V
Parameter Symbol min. H-input voltage L-input voltage H-output voltage L-output voltage Limit Values typ. max. Unit Test Condition Remarks
VIH VIL VOH VOL
3.5 - 0.4 4.5
VDD + 0.4 V
1.5 V V V
XTAL1 XTAL1
0.4
IOH = 100 A CI 60 pF IOL = 100 A CI 60 pF
XTAL2 XTAL2
Capacitances TA = 0 to 70 C; VDD = 5 V 5 %, VSS = 0 V Parameter Symbol Limit Values min. Input capacitance I/O-capacitance Output capacitance Load capacitance
CIN
Unit
Remarks
max. 7 7 25 60 pF pF pF pF All pins except Lla, Llb Lla, Llb XTAL1, XTAL2
CI/O COUT CI
Semiconductor Group
121
Electrical Characteristics
Oscillator Circuits
C LD
XTAL1
External Oscillator Signal
XTAL 1
15.36 MHz 100 ppm
C LD
XTAL 2 N.C. XTAL 2
Crystal Oscillator Mode C LD = 2 x C L - C I/O
Driving from External Source Minimum High Time : 30 ns Minimum Low Time : 28 ns
ITS05374
Figure 54 Oscillator Circuits
XTAL1, 2 Parameter
Recommended typical crystal parameters. Symbol Limit Values 20 7 30 65 Unit fF pF pF
Motional capacitance Shunt Load Resonance resistor
C1 C0 CL Rr
Semiconductor Group
122
Electrical Characteristics
AC-Characteristics Inputs are driven to 2.4 V for a logical `1' and to 0.45 V for a logical `0'. Timing measurements are made at 2.0 V for a logical `1' and 0.8 V for a logical `0'. The AC testing input/output waveforms are shown below.
2.4 V 2.0 V 0.8 V 0.45 V 2.0 V Output 0.8 V
C Load = 100 pF
ITS05375
Figure 55 Input/Output Waveforms for AC-Tests Serial Control Interface Timing
t CSs
CS
t CSh
t CSSDX
SCLK
t CHCH
~ ~
MOSI
t SDRs
MISO
t SDRh
~ ~
MSB
t SDXd
~ ~
~ ~
~ ~
~ ~
t SDXd
t SDXt t SCIl
INT
ITD06341
Figure 56 SCI-Switching Characteristics
Semiconductor Group 123
~ ~
Electrical Characteristics
Parameter
Symbol min.
Limit Values max.
Unit
SCLK-frequency Chip select setup time Chip select hold time MOSI-setup time MOSI-hold time MISO-data-out delay from CS MISO-data-out delay CS high to INT low CS high to MISO-tristate
tCHCH tCSs tCSh tSDRs tSDRh tCSSDX tSDXd tCSIl tSDXt
250 10 0 50 50 150 150 150 30
ns ns ns ns ns ns ns ns ns
Note: The rise time on INT after CS becomes low depends on the external pull-up resistor.
Semiconductor Group
124
Electrical Characteristics
IOM(R)-2 Bus Switching Characteristics
t FSD
FSC
t FSW
t FSD
t DCL t DCLH
DCL
t DCLL
t ODD
DD / DU
t IIH t IIS
DU / DD
t BCD
BCL
t BCD
t SDD
SDSx
~ ~
t SDD
ITD05382
Figure 57 IOM(R)-2 TE-Mode (DCL, FSC output)
Semiconductor Group 125
Electrical Characteristics
Parameter DCL-clock period (1.536 MHz) DCL-duty cycle DCL-width high DCL-width low FSC-period FSC-setup delay FSC-width reduced FSC-length (1 DCL) nominal FSC-length (64 DCL) DU/DD-data-in setup time DU/DD-data-in hold time DU/DD-data-out delay Bit clock delay Strobe delay from DCL
Symbol min.
Limit Values typ. 651 50 326 326 125 - 20 585 50 50 150 - 20 20 120 651 41.6 20 717 max. 717 60 391 391 585 40 260 260
Unit ns % ns ns s ns ns s ns ns ns ns ns
tDCL tDCLH tDCLL tFSC tFSD tFSW tIIS tIIH tODD tBCD tSDD
Note: Reduced FSC-length is output every eighth frame triggered by a CV in the received M-bit.
Semiconductor Group
126
Electrical Characteristics
t DCL t DCLH
DCL
t DCLL
t FS t FH
t FSS
t FLH
FSC
t ODD
DU Bit 1
t H t S
DU/DD Bit 1
ITD05383
Figure 58 TR-, HDLC- Mode (DCL, FSC input)
Semiconductor Group
127
Electrical Characteristics
Parameter DCL-clock period (1.536 MHz) DCL-duty cycle DCL-width high DCL-width low FSC-period FSC-setup time FSC-hold time FSC-setup short1) FSC-hold long2) DU/DD-data-in setup time DU/DD-data-in hold time DU-data-out delay from DCL
Symbol min.
Limit Values typ. 651 50 326 326 125 70 40 70 40 50 50 150 max. 814 70 489 489 488 30 163 163
Unit ns % ns ns s ns ns ns ns ns ns ns
tDCL tDCLH tDCLL tFSC tFs tFh tFSS tFLH tIIs tIIh tODD
Notes: 1) Nominal FSC-length = 1 DCL-period (Trigger for M = CV-generation) 2) No trigger for M = CV-generation
MCLK-Timing
TP
ITT05653
Figure 60 MCLK-Timing Parameter Clock period 0.96 MHz 1.92 MHz 3.84 MHz 7.68 MHz Duty cycle
Semiconductor Group 128
Symbol min.
Limit Values typ. 1042 521 260 130 50 max.
Unit ns ns ns ns %
Tp Tp Tp Tp
Electrical Characteristics
Reset Timings
VHH VHL VDD
~ ~
t min
RST
~ ~ ~ ~
RST
td
tr
td
tr
MCLK
ITD06314
Figure 59 Undervoltage Detection
Parameter
Symbol
Limit Values min. max. 4.4 230 11 1
Unit
Threshold value Hysteresis Minimum voltage drop Delay from VHH crossing to reset active
VHL VHH - VHL Tmin Td
4.2 50
V ms s s
VHL and (VHH - VHL) values are tested at room temperature.
Typical temperature drift is - 8 mV per + 10 C temperature drift for VHL and + 3 mV per + 10 C for the hysteresis value. Components are tested at 75 C at which the absolute minimum VHL-level is set to 4.14 V for pass condition.
Semiconductor Group 129
Electrical Characteristics
6
Package Outlines
Plastic Package, P-DSO-28-1 (SMD) (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 130
Dimensions in mm
GPS05123

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